Category Archives: Semiconductors

wafer revenues decreaseWorldwide silicon wafer revenues declined by 12 percent in 2012 compared to 2011, according to the SEMI Silicon Manufacturers Group (SMG) in its year-end analysis of the silicon wafer industry. Worldwide silicon wafer area shipments declined 0.1 percent in 2012 when compared to 2011 area shipments.

In 2012, silicon wafer area shipments totaled 9,031 million square inches (MSI), down from the 9,043 million square inches shipped during 2011. Revenues totaled $8.7 billion down from $9.9 billion posted in 2011.

"Much like semiconductor unit shipments, semiconductor silicon shipments started out the year strong; however, shipments weakened during the second half of the year,” said Byungseop Hong, chairman of SEMI SMG and director of Global Marketing at LG Siltron. “Despite challenges in the market, 300 mm volume shipments reached record levels.”

Read more: When will the semiconductor industry recover?

Annual Silicon* Industry Trends

 

2007

2008

2009

2010

2011

2012

Area Shipments (MSI)

8,661

8,137

6,707

9,370

9,043

9,031

Revenues ($B)

12.1

11.4

6.7

9.7

9.9

8.7

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or "chips" are fabricated.

This report was compiled and released by the the Silicon Manufacturers Group, which acts as an independent special interest group within the SEMI association. The group’s purpose is to facilitate collective efforts on issues related to the silicon industry, including the development of market information and statistics about the silicon industry and the semiconductor market.

SEMI is the global industry association with over 2,000 members, serving the nano- and microelectronics manufacturing supply chains. 

Imagers

Since 2010, there has been growth beyond expectations in the adoption of mobile devices, such as smart phones and tablets, which has called for larger volumes of CMOS image sensor chips to be produced. The resolution and miniaturization races are ongoing, and performance metrics are also becoming more stringent. In addition to the conventional pixel shrinkage, a “more than Moore” trend is increasingly evident. Resolutions of over 20 Mpixels are commercially available for mobile devices employing enhanced small-size pixels. Thanks to the innovative readout and ADC architectures embedded at the column and chip levels, data rates approaching 50Gb/s and a noise floor below single electron have been demonstrated. In addition to the conventional applications, ultra-low-power vision sensors, 3D, high-speed, and multispectral imaging are the front-running emerging technologies.

Back-side Illumination (BSI) is now the mainstream technology for high-volume, high-performance mobile applications, 1.12μm BSI pixels are available, and the industry is potentially moving towards 0.9μm pixel pitch and below. Additional innovative technologies outside of the traditional scaling include advanced 3D stacking of a specialized image sensor layer on top of deep-submicron digital CMOS (65nm 1P7M) using through silicon vias (TSVs) and micro-bumps. The importance of digital-signal-processing technology in cameras continues to grow in order to mitigate sensor imperfections and noise, and to compensate for optical limitations. The level of sensor computation is increasing to thousands of operations-per pixel, requiring high-performance and low-power digital-signal-processing solutions. In parallel with these efforts is a trend throughout the image sensor industry toward higher levels of integration to reduce system costs.

Ultra-low-power vision sensors are being reported in which more programmability and computation is performed at the pixel level in order to extract scene information such as object features and motion.

Lightfield/plenoptic commercial cameras, which have been available since 2010, are now gaining popularity and are being marketed for 3D imaging and/or all-in-focus 2D imaging. On-chip stereoscopic vision has been demonstrated through digital micro lenses (DML), paving the way to next-generation passive 3D imaging for mobile and entertainment applications, e.g. through gesture control user interfaces.

Significant R&D effort is being spent on active 3D imaging time-of-flight (TOF) applications to support requirements from autonomous driving, gaming, and industrial applications, addressing open challenges like background light immunity, higher spatial resolution, and longer distance range. Deep-submicron CMOS single-photon avalanche diodes (SPADs) have been developed by several groups using different technology nodes. They are now capable of meeting the requirements for high resolution, high timing accuracy by employing highly parallel time-to-digital-converters (TDCs) and small pixel pitch with better fill factor.

Ultra-high-speed image sensors for scientific imaging applications with up to 20Mfps acquisition speed have been demonstrated.

Multispectral imaging is gaining a lot of interest from the image sensor community: several research groups have demonstrated fully CMOS room-temperature THz image sensors, and a hybrid sensor capable of simultaneous visible, IR, and THz detection has been reported.

The share of CCDs continues to shrink in machine vision, compact DSC and security applications. Only for high-end digital cameras for astronomy and medical imaging do CCDs still maintain a significant market share.

Sensors & MEMS

A 4×4 array of sensing cells, developed by Dr. Peng Peng of Seagate Technology, from Flexible Microtactile Sensor for Normal and Shear Elasticity (IEEE Transactions on Industrial Electronics)

MEMS inertial sensors are finding widespread use in consumer applications to provide enhanced user interfaces, localization, and image stabilization. Accelerometers and gyroscopes are being combined with 3D magnetic-field sensors to form nine-degree-of-freedom devices, and pressure sensors will eventually add a 10th degree. The power consumption of such devices is becoming sufficiently low for the sensor to be on all the time, enhancing indoor navigation. There have been further advances in heterogeneous integration of MEMS with interface circuits in supporting increased performance, larger sensor arrays, reduced noise sensitivity, reduced size, and lower costs.

To address the stringent requirements of automotive, industrial, mobile, and scientific application, MEMS inertial sensors, pressure sensors and microphones are becoming more robust against electromagnetic interference (EMI), packaging parasitics, process voltage temperature (PVT) variations, humidity, and vibration.

Sensor interfaces achieve increasingly high resolution and dynamic range while maintaining or improving power or energy efficiency. This is achieved through techniques such as zooming, non-uniform quantization, and compensation for baseline values.

New calibration approaches, such as voltage calibration, are being adopted for BJT-based temperature sensors to reduce cost. In addition to thermal management applications (prevention of overheating in microprocessors and SoCs), temperature sensors are also increasingly co-integrated with other sensors (e.g. humidity, pressure, and current sensors) and MEMS resonators for cross-sensitivity compensation. Alternative temperature-sensing concepts find their way into applications with specific requirements not easily addressed by BJTs: thermal diffusivity-based sensing for high-temperature applications; thermistor-based and Q-based concepts for in-situ temperature sensing of MEMS devices and for ultra-low voltage operation.

MEMS oscillators continue to improve; phase noise is now low enough for demanding RF applications, 12kHz-to-20MHz integrated jitter is now below 0.5ps, and frequency accuracy is now better than 0.5ppm. Consumer applications are adopting new low-power and low-cost oscillators.

Biomedical

There have been continuous achievements in the area of ICs for neural and biopotential interfacing technologies. Spatial resolution of neural monitoring devices is being reduced utilizing the benefits of CMOS technology. IC providers are increasing their component offerings towards miniaturization of portable medical devices.

Telemedicine and remote-monitoring applications are expanding with support from IC manufacturing companies. The applications of such systems are not limited to services targeted for elderly or chronically ill patients; for example there are several technologies developed to enhance the way clinical trials are conducted by monitoring patient adherence and by improving data collection. Low power WiFi, and Bluetooth-low-energy is emerging as a standard wireless connection between portable communication services and wearable technology.

Smart biomolecular sensing is another major trend that marries solid-state and biochemical worlds together with the ultimate goal of enabling a more predictive and preventative medicine. With the help of the accuracy and parallelism enabled by CMOS technology, time, cost, and error rate of DNA sequencing may be significantly improved. Direct electronic readout may relax the need for complex biochemical assays. Similar trends are becoming increasingly evident in the space of proteomics and sample preparation.

Even for medical imaging, there is a trend from hospital imaging toward point-of-care and portable devices. A key example is in the space of portable high-resolution ultrasounds in which larger scientific imaging setups are being integrated onto the sensor by process technology (e.g. integrated spectral filters, CMUT). Another example is in the space of molecular imaging. The advent of silicon photomultipliers (SiPM) providing a solid-state alternative to PMTs enable the realization of PET scanners compatible with MRI, opening the way to new frontiers in the field of cancer diagnostics. More recently, SiPMs realized within deep-submicron CMOS technologies have allowed the integration at pixel- and chip-level of extra features, e.g. multiple timestamp extraction, allowing in perspective a dramatic reduction of the system cost.

Displays

The desire to put much higher-resolution and higher-definition displays into mobile applications is one of the display technology trends, and it is now opening a Full HD smartphone era.  440ppi high-definition displays are expected, even for 5-inch display sizes. Low-temperature polysilicon (LTPS) technology seems to have more merits over a-Si TFT technology. But a-Si TFT and oxide TFT technologies supported by compensating driver systems are being prepared to compete with it. Very-large-size LCD TVs over 84 inches, and UD (3840×2160) resolution are now the leading entertainment systems. 55-inch AMOLED TVs with Full HD resolution are also opening new opportunities in consumer applications.

As touch-screen displays for mobile devices become increasingly thin, capacitive touch sensors move closer to the display. The resulting in-cell touch displays come with reduced signal levels due to increased parasitics, and increased interference from the display and switched-mode chargers. Noise immunity is improved by adopting noise filtering and new signal modulation approaches.

This and other related topics will be discussed at length at ISSCC 2013, the foremost global forum for new developments in the integrated-circuit industry. ISSCC, the International Solid-State Circuits Conference, will be held on February 17-21, 2013, at the San Francisco Marriott Marquis Hotel.

In the second of two installments, Linx Consulting reports a steady growth in semiconductor production, as released in The Econometric Semiconductor Forecast.  The first installment focused on regional developments that will affect semiconductor industry growth.

Semiconductor production to see steady growth after 2013

The weakness in economic growth spills into end products containing semiconductors in 2012 and early 2013.  Our model relating final demands to aggregate semiconductor production (measured by SEMI’s Million Square Inches of silicon processed, MSI) suggests weak demand was anticipated in 2012, and that by early 2013, enough improvement in end markets occurs to push growth up at a modest pace that averages slightly less than 6% for the full year.   By 2014, growth should recover to long-term potential growth for MSI of approximately 7%/year.

 

Figure 1: Aggregate semiconductor production from 1955 to present, with forecast to 2015.

Key assumptions driving this forecast include some solution to the fiscal cliff dilemma that permits US consumers and businesses to begin to return to more normal conditions.  Removing uncertainty drives a modest expansion US spending on technology goods of around 2.3%, up from the anemic 0.8% growth anticipated for 2012.  Most of that growth will occur in the second half of 2013, as it will take some time for businesses to analyze the new policy environment and then implement investment plans.  Inventory-shipment ratios for technology goods, which are spiking in the last half of 2012, are assumed to recede on a steady pace to more typical levels through 2013.  If shipments in IT goods do not develop as expected, the quarterly pattern above would most likely show a steeper decline in 2012Q4 and a further decline in 2013Q1, followed by strong gains in Q2 or Q3.

 

Figure 2: The difference between Segment Demand and Total Silicon Area (includes test and monitor wafers).

Strongest growth will remain in flash memories and logic devices

The overall picture of MSI growth breaks down into the expected performance of device segments and technology nodes.  Despite the shift to consumer electronics and mobile platforms, we expect growth to be concentrated in CMOS products with a continuing slowing of unit growth and analog and discrete devices.  Strongest growth will remain with flash memories, and advanced foundry logic devices targeted at tablets and phones.

In contrast with advanced memory and logic processing, approximately 56% of the market continues to be produced at design dimensions in excess of 100 nm on wafer sizes at 200 mm or smaller.  This market segment is extremely sensitive to economic volatility and has slowed significantly in the last four years.  Manufacturers of these devices are often capital constrained and extremely cost sensitive, leading to little process innovation and limited capacity expansion.

More silicon area at 32 nm produced in 2012 than any other node

On a technology basis, despite tight capital budgets, the introduction of devices at 28 and 22nm half pitches continues apace, and significant process challenges are driving increased complexity and resultant challenges in patterning, cleaning, CMP and deposition throughout the device manufacturing process.  2012 is forecast to have produced more silicon area at 32nm than any other node, and the introduction of low 20nm half pitches and flash has continued to grow startling rates. 

In total devices manufactured at 65nm and below continued to show strong area growth in 2012 of 14%, with devices at 90nm and above largely offsetting declines from 2011 with 8% growth in 2012, but flat performance on average.

 

 

Packaging and assembly are key segments of the growing semiconductor supply chain in China. Based on our tracking of 139 companies, and considering numerous small companies not tracked in detail, there are over 200 companies competing in the packaging and assembly market in China. Although many are small companies manufacturing low-pin count devices, all of the world’s “Top 10” OSAT, Outsourced Semiconductor Assembly and Test, players have one or more assembly and testing facilities in China as shown below. Eight of the world top 10 IDM companies have assembly and test manufacturing facilities in China, and most entered into China earlier than the OSAT players, in the mid-1990s.

Top Ten OSAT Facilities in China

1)    ASE

2)    Amkor

3)    SPIL

4)    STATS ChipPAC

5)    Powertech

6)    UTAC

7)    ChipMOS

8)    JCET

9)    KYEC

10)    Unisem

In addition to the international companies, domestic subcontractor companies are increasingly joining the global outsourcing market. The assembly of small-size optoelectronic chips like CMOS image sensors is the most mature 3D through-silicon via platform at the moment and China players occupy an important place through transferring authorized technology from oversea partners. Also, domestic semiconductor equipment suppliers that previously focused on front-end tool development are applying their products in wafer level package and TSV assembly.

With the growth of semiconductor packaging industry in China, domestic packaging material suppliers are emerging with the industry and are now starting to serve the worldwide leading packaging houses. Given the emphasis on low-cost manufacturing, packaging houses will continue to evaluate China-based suppliers to realize lower material cost. On the other hand, to enhance their competitive power, stabilize sales and marketing channels, and reduce operational risk, China-headquartered material suppliers are forming partnerships with leading packaging houses. In the China Semiconductor Packaging Market Outlook 2012/2013 report, we discuss semiconductor packaging material segment market and supply in China, and include both manufacturing facilities owned by foreign companies and domestic companies. 

In the first of two installments, we examine the global issues facing the semiconductor industry, as released by Linx Consulting in The Econometric Semiconductor Forecast. Part two predicts that semiconductor growth should recover by 2014.

United States’ economic outlook 

The January 1st “fiscal cliff” deadline in the US dominates the near term outlook for the world economy.  ANY settlement will stabilize the situation, but any politically acceptable near term agreement in Washington will not be enough to truly begin to solve the longer-term problems. The political dynamics are not yet in place to lead to a long-term solution to debt restructuring or reducing excessive growth in entitlements. The first fiscal cliff compromise, which includes higher taxes on the wealthier income-earners, elimination of the 2% social security tax reduction, and a permanent fix to the alternative minimum tax levels, gave clarity to consumers on their tax situations. Discretionary and entitlement government spending controls or cuts to reduce government debt burdens were deferred, leaving key questions about policy to later negotiations. That extension of uncertainty will dampen investment spending and government purchases of equipment at least into the first half of 2013. Economic growth will stagnate in the beginning of the year, and then bounce briefly when the new policy environment becomes clear.  Post bounce, the longer term issues will begin to re-surface, and economic growth should settle back into a sluggish trend that lags potential output. This modest growth will be slow to lower unemployment.  Without a strong labor market, businesses will plan for very modest gains in consumer spending, relatively low inflation, and no significant change in interest rates.

Europe’s economic outlook

Most economies are in mild recession, as central governments raise taxes and/or cut spending in attempt to reduce debt. Austerity measures, coupled with potential national bankruptcies in Greece, and recessions in Spain and Italy which will likely extend into early 2014, produce severe stress on euro currency. For the euro to survive, Germany and the most troubled countries will need to compromise national needs to develop an approach that will satisfy financial markets.  France introduces a growing uncertainty to the European outlook. It continues to head in the opposite direction from most countries, expanding the central government’s involvement in the economy, ignoring debt growth, and pushing income redistribution measures which could stifle growth. While the Eurozone should survive intact, the political process will likely keep markets uncertain and most countries’ fiscal budgets austere.  Overall economic activity measured by real GDP most likely will contract slightly in 2013.

Asia’s economic outlook

With key developed world markets in recession or growing weakly, Asian economies will have difficulty producing strong expansions in 2013. With the exception of Japan, however, rates of growth are likely to improve from 2012. Led by China, which moved a bit too aggressively to cool its economy in 2012, policies have become slightly more expansive across the region and should produce slightly stronger real growth rates. Growth will come more from internal regional development than export-led growth.

Risks affecting the semiconductor industry 

Negative risks dominate discussions among serious analysts. In Europe, a financial calamity from either a banking system failure or the breakup of the Eurozone would produce a severe recession with global implications. In the US, an imbalanced solution to the fiscal cliff could stifle growth and tumble the economy into a brief recession. Emerging commodity-focused or dependent economies would be negatively impacted by a weaker Asian expansion. Positive risks, which get very little discussion in popular press these days, include a much sharper boost in the US following a settlement of the “fiscal cliff” dilemma, and a slowly improving European situation (most likely led by Germany or a group of northern European economies) that stabilizes more rapidly the fiscal situation in Europe.  A number of US forecasters surveyed by the National Association for Business Economics on December 17th expect US growth to rebound sharply and exceed 3 ½% by the end of 2013 as the uncertainty “discount” is removed from markets. While an equal number expect growth to stagnate around 1%, the upside should be at least acknowledged as a possible upside risk to the current consensus.

A new econometric semiconductor industry forecast predicts semiconductor wafer area production to grow slightly less than 6% in 2013, according to Linx Consulting.

Using a macroeconomic forecasting tool that incorporates measures of economic uncertainty, global economic shocks, and regional volatility, the forecasting service, called The Econometric Semiconductor Forecast, predicts a slow first quarter in 2013 will be followed by a strong second quarter with moderate growth in the second half of the year. This modest growth forecast is believed to be demand-driven, since inventory levels have not shown a significant increase in 2012.

The Econometric Semiconductor Forecast is the first to use global GDP macroeconomic models to provide semiconductor industry forecasts at a quarterly frequency with monthly updates, allowing forecast recipients to plan for short-term fluctuations in the volatile semiconductor industry.

“An unstable global economy leads to wide variations in economic forecasts, making it difficult to develop meaningful demand-side forecasts,” said Mark Thirsk, managing partner of Linx Consulting. “Our econometric forecast model allows us to develop more accurate forecasts on a monthly and quarterly basis, which are vital for operations planning and business forecasting in the semiconductor supply chain.”

Based on a demand-driven equation that captures >98% of the long run variation in semiconductors, the economic forecast model used by Linx Consulting includes global real GDP growth from consensus forecasts, US consumer and business spending on technology goods, inventory-shipments ratio, computer and electronics, and financial crisis shock indicator to capture panic behavior in the latest cycle.

Headwinds in the Global Economy

Uncertainty surrounding government policies and ongoing fallout from the financial crisis combine to restrain growth in 2013. Protracted periods of uncertainty followed financial crises in the past, accompanied by prolonged subdued growth rates as major economic policies changed and debt restructuring dampened investment and spending.  Few of today’s policymakers or business leaders have experience dealing with this type of an environment. That lack of experience adds to the uncertainty in the current outlook, as it tends to increase cautious economic behavior by consumers and businesses. In 2013, policies should become a bit more settled in the first half of the year, improving confidence somewhat.  Global economic growth is unlikely to recover to its longer-term potential until after 2013 as fundamental structural imbalances will improve slowly at best.

In the face of these headwinds, the more than 250 forecasters surveyed in the December 2012 Consensus Forecasts produced a consensus subdued, below-trend global growth of 2.6% in 2013.  This is a slight improvement over the 2.5% now expected for 2012, but less than the 3.1% achieved in 2011 and below the long-term potential real global growth rate of around 3.5%.  While the consensus averages to 2.6% for 2013, there is a relatively wide range in individual forecasts, reflecting the uncertainty in the outlook.  Individual outlooks depend most on how forecasters see developments in the US and Eurozone.

Read more from The Econometric Semiconductor Forecast: Regional developments to affect growth of semiconductor industry

The forecasting service will provide subscribers with monthly updates of quarterly forecasts of total semiconductor production in Million Square Inches of silicon processed, as well as segmentation by device, including DRAM, flash, MPU, ASIC, analog and discrete.

 

TU DresdenTechnische Universität (TU) Dresden announced Monday the successful initial operation of a low-power test chip featuring a Tensilica Xtensa LX4 DSP equipped with RacyICs power management IP implemented in GLOBALFOUNDRIES’ advanced 28nm Super Low Power, or SLP, technology. The chip is able to operate in a wide voltage and frequency range from 0.7V to 1.1V and 90 MHz to 1 GHz. Within that range, the optimal voltage/frequency combination is determined adaptively based on a new hardware performance monitor concept. The complete baseline IP was developed by the university team, who also did logic synthesis, place and route and sign-off of the test chip.

"Our ability to successfully realize microchips in advanced technologies is a result of a long-term strategy to build an experienced team, which covers all aspects of analog, digital and mixed-signal IC design," stated Professor René Schüffny, TU Dresden. "This accumulated engineering competence is one key enabler for TU Dresden’s leading-edge research in the field of complex systems based on advanced electronics."

The chip has been developed within the frame of the CoolRF28 project. This project is part of the Leading-Edge Cluster "Cool Silicon," which is sponsored by the German Federal Ministry of Education and Research, or BMBF, within the scope of its Leading-Edge Cluster Competition. In the "Cool Silicon" cluster, universities, research institutes, small and medium enterprises, or SMEs, and big corporations closely cooperate in numerous projects on the next generation of energy-efficient electronics.

"We’re very impressed by the high research and engineering competence of the TU Dresden team," stated Frank Dresig, GLOBALFOUNDRIES’ European Field Engineering Manager. "The chip directly shows the capabilities of our advanced 28nm SLP process for implementation of ultra low-power SoCs for consumer applications."

The test chip’s power management is based on an IP for adaptive voltage and frequency scaling provided by RacyICs, a start-up company offering design and implementation services.

"The close cooperation with TU Dresden and GLOBALFOUNDRIES helps us to develop world-class services and IP products in advanced technology nodes," stated Holger Eisenreich, RacyICs’ Managing Director. "Because of high risks and costs, it is almost impossible for SMEs to enter this market without such cooperation."

With assistance from Tensilica, the university team integrated an Xtensa LX4 DSP core to demonstrate the overall power reduction benefits from the combination of a 28nm low-power technology, adaptive power management and an advanced processor IP core.

"Tensilica has had a long-standing relationship with the researchers at TU Dresden and congratulates them on this successful design effort," stated Chris Rowen, Tensilca’s CTO. "Tensilica’s Xtensa processor is a fundamental building block in TU Dresden’s wireless communications architecture, and we are working together to proliferate know-how on configurable architectures to the worldwide design community."

Technische Universität Dresden, founded in 1828, is a full-scale university with 14 faculties, covering a wide range of fields in science and engineering, humanities, social sciences and medicine. TU Dresden has about 36,500 students and almost 5,319 employees with 507 professors among them, and is the largest university in Saxony today. 

Integration is a feature we all look for in our electronic devices. Information readily available on our smart phones is integrated with web-based services and with our personal data on our home computer.  This interoperability that we take for granted is thanks to common software and hardware platforms that are shared by all the elements of this system. Platforms surround us everywhere in our daily lives – the specific model of the car we drive is built on a platform, the electrical systems in our house are on a platform: 110/220V with universal plugs. Platforms?! So I got curious and looked up a more formal definition on Wikipedia:

Platform technology is a term for technology that enables the creation of products and processes that support present or future development.

Why has the concept of platforms been on my mind? Because I hear it more and more often from engineers in the trenches of the post-tapeout flow – people who develop the data preparation sequences that ready their design for manufacturing. They say it is getting increasingly complicated to accommodate all the functional requirements and still meet the TAT (turn-around-time) requirements.  The 20nm node adds additional complexity to this flow – beyond retargeting, etch correction, fill insertion, insertion of assist features and the application of optical proximity correction– now decomposition-induced steps are required and replicate some of the steps for both layers.  Industry standards like the OASIS format enable the communication between independent standalone tools, but are not enough to enable extension in new functional areas and maintain a steady overall runtime performance. Users have to be familiar with all the features and conventions for each tool – not an efficient way to scale up an operation.

The oldest and most versatile platform in computational lithography is Calibre. It started with a powerful geometry processing engine and a hierarchical data base and is accessed through an integrated scripting environment using the Tcl-based  standard verification rule format (SVRF) and the Tcl verification format (TVF). As the requirements for making a design manufacturable with available lithography tools has grown, so has the scope of functionality available to lithographers and recipe developers. APIs have expanded the programming capabilities: the Calibre API provides access to the data base, the lithography API provides access to the simulation engine, the metrology API enables advanced programming of measurement site selection and characterization, the fracture API enables custom fracture (Figure 1). All of these functions let you both build data processing flows that meet manufacturing needs and encode your very own ideas for the most efficient data processing approach. The additional benefit of a unified platform is that it also enables the seamless interaction and integration of tools in a data processing flow. If you can cover the full flow within one platform, rather than transferring giant post-tapeout files between point tools, you will realize a much faster turn-around time.

Common workflow
Figure 1: All tools in the Calibre platform are programmed using the SVRF language and tcl extensions and can be customized via a number of APIs – maintaining a common and integrated workflow.

A platform like Calibre is uniformly used in both the physical verification of the design and in manufacturing, so that innovation entering the verification space flows freely over to the manufacturing side without rework and qualification. Examples include the smart fill applications and the decomposition and compliance checks for double-patterning (DP).

The benefits to using a unified software platform in the post-tapeout flow, illustrated in Figure 2, are also leveraged by the EDA vendor—our software developers use the common software architecture in the platform for very fast and efficient development of new tools and features. This reduces the response time to customer enhancement requests. New technology, like model-based fracture and self-aligned double patterning (SADP) decomposition, were rapidly prototyped based on that.

Calibre workflow
Figure 2: Benefit and scope of a platform solution and the support level provided by Calibre.  

 

A platform not only provides the integration and efficient operation at the work-flow level, but it also enables efficiency at the data-center level, considering the simultaneous and sequential execution of many different designs and computational tasks. The tapeout manufacturing system is a complex infrastructure of databases, planning, and tracking mechanisms to manage the entire operation. Common interfaces into the tools used –which are guaranteed by a platform solution–let you track data and information associated with each run and manage interactions and feedback across different jobs.  This leads, for example, to an improved utilization of the computer system overall as well as better demand and delivery forecasting. Operating a manufacturing system requires a different level of support than single tool solutions and the necessary infrastructure has evolved with the development of the components.

Once you start using a unified platform in your post-tapeout flow, you will see how the platform expands and grows. For today’s sub-nanometer technologies, a powerful and flexible platform for computational lithography is part of a successful business strategy.

Author biography

Dr. Steffen Schulze is the Product Management Director for the Mentor Graphics’ Calibre Semiconductor Solutions. He can be reached at [email protected].

ISMI to partner with Araca


February 6, 2013

SEMATECH announced today that Araca Inc., a leading provider of products and services for chemical mechanical planarization (CMP) research and development, and the International SEMATECH Manufacturing Initiative (ISMI) are partnering to deliver CMP processing and productivity solutions to help chip manufacturers increase yields, reduce equipment downtime and lower consumables costs.

“Leading-edge device designs and materials are introducing more complexity into planarization processing for manufacturers. This is increasing wafer costs and impacting die yields,” said Dr. Ara Philipossian, president and founder of Araca, Inc. "Partnering with ISMI allows us to validate our CMP Slurry Injector System (SIS-x) and other innovations in high-volume manufacturing facilities across the industry. This technical collaboration with the industry’s leading device manufacturers is vital to our success as we develop and commercialize high-performing and cost-effective CMP solutions.”

As a part of ISMI’s Manufacturing Technology program, Araca and ISMI will evaluate Araca’s CMP SIS-x system on varying consumable set-ups on select types of CMP equipment at ISMI members’ manufacturing locations to help increase removal rates while reducing polishing defects and slurry consumption for CMP processes.

“Cost and productivity are major obstacles in CMP, in addition to eliminating process variables that arise from equipment generated variation. While this applies equally to new and legacy processes, this is especially true for sub-20 nm high-volume manufacturing,” said Boyd Finlay, ISMI project manager.

ISMI is working cooperatively with the semiconductor industry to provide solutions to common high-volume productivity and cost detractors. ISMI’s Manufacturing Technology Program leads various equipment productivity improvement projects including CVD/PVD/etch particle elimination, CVD pump failures and chamber dusting prevention, electrostatic chuck cost-of -ownership, equipment variation and control, and defect source and root cause analysis.

ISMI also provides industry leadership through the ESH Technology Center, focusing on sustainability and green initiatives, addressing regulatory issues, and resource conservation in manufacturing operations.

ISMI membership is open to all semiconductor manufacturers and suppliers. ISMI and its members collaborate with a broad network of companies, consortia, universities, national laboratories, and associations from around the world to tackle manufacturing and ESH technology challenges.

Microchip Technology Inc. introduced three new SPI Flash memory devices yesterday. The devices, named the SST25PF020B, SST25PF040B and SST25PF080B, offer two, four and eight Mbit of memory and are manufactured with Microchip’s high-performance SuperFlash technology, a split-gate, NOR Flash design with thick-oxide tunneling injector for superior quality and reliability.

“With their extended voltage, smaller footprint and low power consumption, this SST25PFXXXB SPI Flash family provides designers with even simpler, more economical and more innovative memory solutions for their embedded designs.”

With their extended operating voltage range from 2.3 to 3.6V, extremely low power consumption, small-footprint packaging, and fixed super-fast program and erase times, these SPI Flash memory devices excel in a variety of applications. The memory is partitioned into uniform 4 Kbyte sectors, and 32 and 64 Kbyte blocks, offering flexible erase capabilities and seamless partitioning for program and data code in the same memory block. All three devices enable designers to reduce their overall product design cycles and total system costs while improving product performance. The extended voltage range provides designers with a wider set of options on the power-supply voltage for their chipsets and board designs, and reduces overall power consumption, making these memory devices especially well-suited for battery-operated accessories, sensors and equipment.

The SST25PF020B, SST25PF040B and SST25PF080B SPI Flash devices offer flexible erase and program performance, including erasing sectors and blocks as fast as 18 ms, erasing the entire Flash memory chip in 35 ms, and a word-programming time of 7 µs using Auto Address Increment (AAI). The devices also offer superior reliability of 100,000 endurance cycles, typical, and greater than 100 years of data retention. The active read current of these devices is only 10 mA, typical, at 80 MHz, and standby current is only 10 µA, typical.

All three devices excel in a broad range of applications, including those in the consumer-electronics and industrial markets. Examples of ideal end applications include smart meters, wireless products for sports/fitness/health monitoring, digital radios, low-power Wi-Fi® products, GPS, and a wide array of battery-operated products. Additionally, these SPI Flash memory devices are well suited for use in medical applications, such as glucose meters, hearing aids and wireless sensors.

“Newer designs requiring greater mobility, along with more compact form factors, are driving lower-power and extended-voltage requirements,” said Randy Drwinga, vice president of Microchip’s SuperFlash Memory Division. “With their extended voltage, smaller footprint and low power consumption, this SST25PFXXXB SPI Flash family provides designers with even simpler, more economical and more innovative memory solutions for their embedded designs.”

Pricing & Availability

The SST25PF020B starts at $0.53 each, in 8-lead 150 mil SOIC, 8-contact USON (3×2 mm), or 8-contact WSON (6×5 mm) packages, in 10,000-unit quantities. The SST25PF040B starts at $0.66 each, in 8-lead 150 mil SOIC, 8-lead 200 mil SOIC, or 8-contact WSON (6×5 mm) packages, in 10,000-unit quantities. The SST25PF080B starts at $0.81 each, in 8-lead 150 mil SOIC, 8-lead 200 mil SOIC, or 8-contact WSON (6×5 mm) packages, in 10,000-unit quantities.