Category Archives: Top Story Right

October 2, 2012 – Researchers at the U. of Illinois have devised a method to monitor a semiconductor surface as it is etched, in real time, with nanometer precision.

The new method, dubbed "epi-diffraction phase microscopy" (epi-DPM), is purely optical, and thus noncontact, so researchers can monitor the entire wafer at once instead of point-by-point. It’s faster, lower in cost, and less noisy than the widely used methods of atomic force microscopy or scanning tunneling microscopy, which can only compare before/after etch measurements, the researchers say.

In their work, a grayscale image is shined via projector onto the sample being etched, enabling creation of complex patterns quickly and easily, and the ability to adjust them as needed. "The idea is that the height of the structure can be determined as the light reflects off the different surfaces," stated electrical and computer engineering professor Lynford Goddard, who co-led the group with fellow electrical and computer engineering professor Gabriel Popescu. "Looking at the change in height, you figure out the etch rate. What this allows us to do is monitor it while it’s etching. It allows us to figure out the etch rate both across time and across space, because we can determine the rate at every location within the semiconductor wafer that’s in our field of view."



A three-dimensional image of an etched GaAs semiconductor in a wet etch
solution, taken during etching with the new "epi-diffraction phase microscopy"
(epi-DPM) technique. The height difference between the orange and purple
regions is about 250nm. (Photo by Chris Edwards, Amir Arbabi, Gabriel
Popescu and Lynford Goddard)   And here’s a video describing the process.

Besides monitoring the etching process, the light also catalyzes the etching process itself ("photochemical etching"), a process already used in place of chemical etching on curved features or other shapes. It eliminates the problem of using expensive masks to pattern light through by degrees — and requiring new masks for every tweak of the chip features to achieve correct patterning. "Because our technique is controlled by the computer, it can be dynamic. So you can start off etching one particular shape, midway through realize that you want to make some change, and then change the projector pattern to get the desired outcome," Goddard said.

Beyond semiconductor etching, the researchers see applications for real-time monitoring of other processes in materials and life sciences, e.g. observing carbon nanotubes self-assembly, error monitoring during large-scale computer chip manufacturing, or ensuring precise equipment calibration. Their work, funded by the National Science Foundation, appears in the Sept. 28 journal Light: Science and Applications. Here’s a snippet:

We present epi-diffraction phase microscopy (epi-DPM) as a non-destructive optical method for monitoring semiconductor fabrication processes in real time and with nanometer level sensitivity. The method uses a compact Mach–Zehnder interferometer to recover quantitative amplitude and phase maps of the field reflected by the sample. The low temporal noise of 0.6nm per pixel at 8.93 frames per second enabled us to collect a three-dimensional movie showing the dynamics of wet etching and thereby accurately quantify non-uniformities in the etch rate both across the sample and over time. By displaying a gray-scale digital image on the sample with a computer projector, we performed photochemical etching to define arrays of microlenses while simultaneously monitoring their etch profiles with epi-DPM.

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September 28, 2012 – Want another snapshot of who’s leading the pack among pure-play foundries, and who’s falling off the curve? Look more closely at <45nm offerings, as framed by a recent analysis from IC Insights.

Overall, total pure-play IC foundries will register about 30% of their sales in <45nm process technologies, up from 22% in 2011, IC Insights calculates. Older (>0.18μ) technologies will account for 13%, down from 14% in 2011 and 15% in 2010.

GlobalFoundries, which earlier this year passed UMC to become the No.2 foundry, has rapidly narrowed the technology gap enjoyed by TSMC over its foundry rivals. GF actually has had a significantly higher percentage of its sales coming from 45nm and below process technologies than TSMC (55% vs. 26% in 2011, 65% vs. 37% in 2012), thanks to its MPU-centric focus. TSMC’s still far ahead in terms of actual dollars ($3.8B vs. $1.9B in 2011, $6.2B vs. $2.8B in 2012).

In contrast, look at the next two "Big 4" pureplay foundries: UMC’s <45nm technology generated 6% of sales ($243M) in 2011 and 11% ($427M) in 2012, while SMIC has gotten less than 1% in both years ($1M and $6M). IC Insights thus connects the dot from <45nm sales, through the metric datapoint of revenue/wafer, and into profit margins. (To be fair, UMC is skipping 45nm and offering a 40nm process.)

That lead for TSMC and GlobalFoundries is widening more now that 28nm devices are starting to emerge. "Although many of the pure-play foundries other than the Big 4 focus on specialized processes and technology, the process technology gap between the other significant pure-play IC foundries and the leading-edge producers is enormous," IC Insights notes. Beyond UMC and SMIC who are falling behind, of the next 14 pureplay foundries only four (TowerJazz, Grace/HHNEC, Dongbu, and Xinxin) are expected to have even limited <90nm capabilities this year. Their total overall sales will amount to $4.6B, only about 15% of the total pureplay IC foundry market.

What’s the takeaway from all this? Successful (i.e., profitable) foundries will be the ones "at the leading edge of the process technology roadmap," IC Insights says. (Note that GlobalFoundries is already talking about its 14nm FinFET technology coming in 2014, barely a year after its new 20nm process.) And for all chip companies, those who have the money have the ability to invest in R&D as required to keep up with more complex IC designs and new process technologies.

Major pure-play foundry comparisons. (via IC Insights)

September 25, 2012 – A three-year European project to research solution-processable materials for OLEDs has concluded, with newly developed materials that can be integrated into large-surface OLED components and are suited for printing processes.

The NEMO (NEw Materials for OLEDs from solutions) project, a consortium of 11 companies led by Merck, was formed in Nov. 2009 with backing from the German Federal Ministry of Education and Research (BMBF), to explore a variety of OLED materials and capabilities: soluble light-emitting materials, charge transport materials, new adhesives for reliable encapsulation of each OLED component. Physical tests were included to understand more about the materials for future development work. The project’s total budget was €29M (roughly US $38M).

"The success of the project is an enormous and important step for printable material systems with very good performance data," stated Dr. Udo Heider, head of the OLED unit at Merck. "We are enabling our customers to use cost-efficient manufacturing processes, which thanks to their low material losses in production, will ultimately also benefit the environment."

Results of the project include Merck’s development of a new phosphorescent materials for red, green and blue applications — increasing lifetime extrapolated to 50% of initial brightness (i.e., stability in use) of green triplet emitter materials from 10,000 hours to more than 200,000 hours, and increasing the efficiency of these materials from 30 cd/A up to more than 70 cd/A (candela/ampere) at a brightness of 1000cd/m2.

Here’s a list of other results achieved by the NEMO project’s four industry companies and seven research institute/academic groups:

Humboldt University of Berlin: Modular synthesis strategies were used to produce and test new electron transport materials.

DELO Industrie Klebstoffe: Development of adhesives with low water vapor permeation for flat encapsulation. A main focus of the work was on optimizing the compatibility of the adhesive with the OLED materials. Suitable adhesive systems were identified, and a significant reduction in component defects was achieved. The developed systems were extensively characterized.

Enthone GmbH (formerly Ormecon): Developed dispersions of polyaniline, an electrically conductive polymer, from which charge carrier layers for OLEDs were produced. These displays show electrical properties equivalent to those of the previously used material. For OLED component characterization, impedance spectroscopy was used to investigate the OLEDs prepared by Merck. It was possible to identify unstable areas, which are responsible for the short lifetimes of OLEDs. Additionally, the impedance measurements were used to predict the lifetime of displays.

Fraunhofer Institute for Applied Polymer Research (IAP): Developed polymer-based phosphorescent systems for green and red Merck emitters. Suitable charge transport molecules were bonded as a side group to a main polymer chain. It was possible to demonstrate that this leads to comparable or even better performance parameters and lifetimes of OLEDs in comparison with solution-processable small molecules. For "green", energy efficiencies of 61 cd/A and lifetimes of 66,000 h @ 1000 cd/m2 were achieved.

Heraeus Precious Metals GmbH & Co. KG (formerly H.C. Starck Clevios GmbH): Developed new materials for the intermediate layers, which will improve the charge carrier injection from the anode into the OLED emitter layer and help to increase the lifetime of the components. The work function of the hole injection layers can be set to a specific target value within a wide range of 4.8-6.1 eV. Water-soluble polymer counterions have been developed, which have helped to realize dehydrated PEDOT materials for the first time.

In parallel to this, work was conducted on transparent electrodes that can be separated from solution and are expected to lower the costs of OLEDs. The conductivity of the PEDOT:PSS films was further increased. Initial ITO-free OLED lamps have been realized. In combination with screen printed silver lines, this enables the production of OLEDs for lighting application without any identifiable decrease in luminance from the edge to the center of the component.

University of Potsdam: Studied physical properties such as charge carrier transport and excitation dynamics in newly synthesized materials and in the finished component. In combination with stationary and transient simulations, information was obtained on what processes restrict the efficiency of light emitting diodes and which ones impact component aging.

University of Regensburg: One working group, led by Professor Yersin, developed new emitter classes with both strong and weak metal-metal interactions that show a singlet harvesting effect. It is thus possible to realize highly efficient emitters for OLEDs based on highly economical copper clusters. This work on singlet harvesting with newly developed emitters made from copper clusters was recognized in April 2012 with an innovation prize at the international SPIE Organic Photonics conference in Brussels.

Another working group (led by Professor König) synthesized emitter libraries in accordance with a simple combinatorial protocol. A screening system was developed for the rapid and virtually automated identification and characterization of individual emitters as well as photostability testing thereof. This made it possible to investigate the degradation behavior of many substances and to draw conclusions on various degradation mechanisms.

University of Tübingen: Two groups from Tübingen provided new metallorganic cluster compounds that can be used as luminescent molecules in OLEDs. In chemical synthesis, coordination compounds of the metals rhodium, iridium, palladium, platinum, copper, silver and gold were presented and characterized, giving rise to new, highly promising lead structures for emitter materials.

September 2012 – Even with the persistent troubles in global economics and various technology hurdles in advanced semiconductor manufacturing, IC market growth will continue to improve — and the key is a shift away from what’s been driving the market dynamics, explains IC Insights.

IC unit shipments have been the bedrock of growth in the IC industry for the past 15 years, underpinning roughly a 5% annual growth rate. But that rate will slow to 7% per year due as slowing global GDP weighs down demand, even as users demand electronic gadgets with more capabilities necessitating more capabilities crammed onto a single chip.

But the firm still sees the IC market expanding its long-term growth rate over the next 10 years to an 8% CAGR, because it thinks IC average selling prices (ASPs) will offset that slowing unit growth. IC ASPs actually declined an average of -4% per year for the past decade and a half, but are seen swinging to an average of 1% growth/year from 2011-2021, for an 8% CAGR.

Behind this shift, the firm explains, are four main factors:

  • No new entry-point opportunities. Door’s closed to new manufacturing startups. (It’s a familiar refrain from the firm’s leader, Bill McClean.) That means less irrational overspending in new fabs.

  • Fab-lite foundry model lives on. Another factor in reducing the exuberant overspending in IC fab capacity.

  • Capex/sales narrowing. Despite the technical challenges to be overcome, capex as a percentage of sales continues to shrink: from 21% in 2011 to 19% in 2012, and likely 15% by the end of the decade, the firm projects.

  • 450mm transition is delayed. Chipmakers have long seen a transition to 450mm wafers as their next major cost stepdown reduction — but now they have a lot of competing balls in the air: EUV, new processes, next-gen transistor structures (e.g. 3D), incorporation of new materials. Something’s got to give.

Year IC unit shipments IC average selling price IC market
1996 49.4 $2.49 $122.8
2011 192.7 $1.37 $264.0
1996-2011 CAGR 9.5% -4.0% 5.2%
2021F 380.0 $1.51 $573.8
2011-2021F CAGR 7.0% 1.0% 8.0%

IC market to show better growth. Unit shipments in
billions, IC market in US $B. (Source: IC Insights)

Overlay error is the offset in alignment between pattern at one step of a semiconductor process and pattern at the next step. Traditionally overlay error has referred to successive device layers, but in the case of double-patterning lithography, overlay error may stem from interwoven patterns at the same layer. Regardless, controlling overlay error is one of the most difficult issues that lithography engineers face in this era of shrinking design rules and complex, advanced lithography techniques. Because overlay error can affect yield, device performance and reliability, it must be measured precisely, and all sources of systematic overlay error must be discovered and addressed. These may include mask pattern placement error, deviations from wafer planarity, scanner nonlinearities and process variation.

In most cases, overlay error is measured optically by capturing an image of a specially designed alignment mark called an overlay target. Half of the overlay target is printed during the first process step, and the other half of it is printed during the second process step.

 

A standard overlay target is printed in two steps,  indicated in red and blue, and structured to measure the errors in x and y.

An overlay metrology tool captures the image and quantifies the alignment between the first and second parts of the target. The result is reported as a vector quantity, having a magnitude and direction corresponding to the x and y offsets. The procedure is repeated for each of the overlay targets on the wafer. Overlay error maps are comprised of a circular field of tiny vectors, representing the overlay error across the wafer. These maps are used to adjust the scanner or to uncover issues with the mask pattern, the wafer shape or the process. Overlay error maps are also used to disposition wafers.

Flexible, robust multi-layer target allows simultaneous measurement of overlay error within the same layer and between layers.

A recent development in the area of overlay measurement is extension of measurement capability to new layers and new materials (see above). When overlay error between layers is measured, the optical properties of the top layer are critical to the quality of the data. The metrology tool needs to be able to send photons through the top layer to detect the pattern underneath, and the quality of the image of the buried pattern is critical to the quality of the overall measurement. Because semiconductor processes use a variety of materials, and the optical absorption of a given material generally varies with wavelength, the well-equipped metrology system can select from a variety of wavelengths to achieve sufficient image quality for the buried pattern to enable an accurate, repeatable measurement. The alternative—introducing an extra process step to etch a “window” in the top layer before patterning it—adds significant cycle time and may degrade the underlying pattern. Cycle time pressures are ever-present and well known. Furthermore, when the entire overlay error budget is limited to a small number of nanometers, lithographers cannot afford to allot a large portion of the budget to uncertainty in the output of the overlay metrology tool.

Examples of particularly challenging classes of materials are those used to build 3D transistors, and hard mask materials used during litho-etch-litho-etch lithography. Hard mask materials are opaque to visible light, and their optical properties may fluctuate with composition and even with annealing temperature.  The latest overlay metrology systems can provide an appropriate wavelength that penetrates the top layer, making overlay metrology feasible without additional process steps.

Another new development in the field of overlay metrology is the use of multi-layer overlay targets. New target designs now allow a lithography engineer to measure within-layer overlay and between-layer overlay using one target. These innovative targets are small enough to be inserted into the die without consuming an unfeasible amount of valuable real estate. Their designs are flexible and robust, allowing adjustments for specific process and layer requirements. They are compatible with various pitch-splitting and double-patterning schemes. Most importantly, the new multi-layer targets allow lithographers to measure within- and between-layer overlay error with one image and, at the same time, reduce systematic errors that could degrade the measurement if separate targets had been used.

Overlay metrology remains one of the most challenging issues that lithographers currently face. Innovations in overlay metrology tool and target design must continue, to enable our industry to make smaller, faster, lower power, more affordable chips.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Amir Widmann is a senior director in the Optical Metrology division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

The 58th annual International Electron Devices Meeting (IEDM) will take place December 10-12, 2012 at the San Francisco Hilton Union Square, preceded by a full day of Short Courses on Sunday, Dec. 9 and by a program of 90-minute afternoon tutorial sessions on Saturday, Dec. 8.

Highlights of the IEDM 2012 technical program, which comprises some 220 presentations, include Intel’s unveiling of its industry-leading trigate manufacturing technology; a plethora of advances in memory technologies from numerous companies; IBM’s demonstration of high-performance logic technology on flexible plastic substrates; continuing advances in the scaling of transistors to vanishingly small sizes, and breakthroughs in many other areas that will continue to move electronics technology forward.

“The IEDM can be a crystal ball looking into the future of technology evolution. Leading-edge technologies and novel devices reported at the conference will shine light on the industrial mainstream in the next three-to-five years,” said Tzu-Ning Fang, IEDM 2012 Publicity Chair and Senior Member, Technical Staff, at Spansion, Inc. “This year’s program shows a tremendous amount of work being done in emerging technologies, including novel materials such as molybdenum sulfide, new structures, 3D NAND memories, wider use of III-V materials, MRAM, nanowires and more.”

Besides the IEDM technical program, attendees will enjoy evening panel sessions, Short Courses, award presentations and other events, as follows:

90-Minute Tutorials — Saturday, Dec. 8

Back by popular demand for the second year, the IEDM will hold 90-minute tutorial sessions on emerging topics presented by experts in the fields. They are meant to bridge the gap between established textbook-level knowledge and the leading-edge research as presented during the conference. The tutorial sessions will be presented in parallel in two time slots. Advance registration is required.

2:45-4 p.m.

High Mobility Channel CMOS Transistors – Beyond Silicon by Shinichi Takagi, University of Tokyo

Fundamentals of GaN Based High Frequency Power Electronics by Tomas Palacios, M.I.T.

Spintronics for Embedded Non-Volatile Electronics by Tetsuo Endoh/Tohoku University and Arijit Roychowdhury/Intel

4:30-6:00

2D semiconductors – Fundamental Science and Device Physics by Ali Javey, University of California, Berkeley

Scaling Challenges of Analog Electronics at 32nm and Beyond by Mustafa Badaroglu/IMEC and Bram Nauta/University of Twente

Beyond Charge-Based Computing by Kaushik Roy, Purdue University

Short Courses — Sunday, Dec. 9

The IEDM offers two day-long short courses on Sunday, prior to the technical sessions. They provide the opportunity to learn about emerging areas and important developments, and to benefit from direct contact with expert lecturers. Advance registration is required. This year’s courses are:

Emerging Technologies for Post-14nm CMOS

Circuit and Technology Interaction

Plenary Presentations — Monday, Dec. 10

IEDM 2012 will open on Monday, Dec. 10 at 9 a.m. with three plenary talks:

Flexible Bio-Integrated Electronics by John A. Rogers, University of Illinois

State of the Art and Future Prospects in Display Technologies by Joo-Tae Moon, Senior VP, Director R&D Center, Samsung Display Company

Ultimate Transistor and Memory Technologies: Core of a Sustainable Society by Luc Van den hove, CEO and President IMEC

Emerging Technologies Session — Tuesday morning, Dec. 11

This year’s Emerging Technologies session is on the topic Spintronics: Magnetic Materials and Device Applications, organized by Stefan De Gendt of IMEC. Invited speakers from academia and industry will discuss the challenges, prospects and recent advances in spin-based technology, devices and systems. Following the discovery of the giant magnetoresistance (GMR) effect more than a decade ago, this field has witnessed a veritable revolution encompassing materials and physical phenomena. Electronic devices based on spin transport are expected to play a major role in future information and communication technologies, as spintronic devices will use the spin degree of freedom to store, transport and process information. Papers in this session are:

Spin Transport in Graphene: Fundamental Concepts and Practical Implications by Abdelmadjid Anane et al, Unité Mixte de Physique CNRS/Thales

Thermal Spin Transport and Applications by S. Y. Huang et al, Johns Hopkins/National Tsing Hua University/Academia Sinica

Progress of STT-MRAM Technology and the Effect on Normally-Off Computing Systems, by H. Yoda et al, Toshiba

 Spin Transport in Metal and Oxide Devices at the Nanoscale, by Subir Parui et al, Zernike Institute for Advanced Materials

Error Immunity Techniques for Nanomagnetic Logic, Brian Lambson et al, University of California, Berkeley/Lawrence Berkeley National Lab

Boolean and Non-Boolean Computation With Spin Devices, Mrigank Sharad et al, Purdue University

Luncheon Presentation — Tuesday, Dec. 11

The IEDM Luncheon presentation will be given by Ajit Manocha, CEO of GLOBALFOUNDRIES, Inc., on the topic Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!

Evening Panel Sessions — Tuesday evening, Dec. 11

The IEDM will offer attendees two evening panel discussions. Audience participation is encouraged, with the goal of fostering an open and vigorous exchange of ideas. The panel topics are:

"Will Future Non-Volatile-Memory Contenders Disrupt NAND?" moderated by Al Fazio, Intel

 “The Mighty Little Transistor: FinFETs to the Finish or Another Radical Shift?” moderated by Suresh Venkatesan, GLOBALFOUNDRIES.

Entrepreneurs Lunch — Wednesday noon, Dec. 12

New for 2012 is an entrepreneurs lunch. The speaker will be Weili Dai, cofounder of Marvell Technology Group and Vice President and General Manager of Marvell’s Communications and Consumer Business. One of the most successful women entrepreneurs in the world, she was named No. 89 on the Forbes list of “The World’s 100 Most Powerful Women” earlier this year.

Further information

For registration and other information, interested persons should visit the IEDM 2012 home page at www.ieee-iedm.org.

September 14, 2012 – Now that the initial dust has settled after Apple’s debut of the new iPhone 5, industry watchers are taking a tally of which semiconductor suppliers stand to gain in the newest must-have smartphone.

Below is a quick tally of the key features and which suppliers likely benefit. (As usual teardown firms prepare their knives, TechInsights has cooked up a preliminary calculation of the iPhone 5’s bill-of-materials.)

— Dual-band WiFi. 4G LTE connectivity, which dramatically accelerates speeds vs. previous models This technology (similar to what the Kindle Fire now uses) increases test times at the module test level, which is a sweetspot for TER’s Litepoint business, points out Credit Suisse’s Satya Kumar. TER already indicated that this unit already saw a boost in 2Q12 attributable to both the iPhone 5 and Kindle Fire. Going forward, this likely means other smartphone vendors will adopt this technology, and eventually 802.11ac next year — both of which "are particularly test-intensive" and thus positives for TER, he notes.

Barclay’s CJ Muse, meanwhile, calls out Qualcomm’s 28nm 4G/LTE baseband and Broadcom’s 40nm WiFi combo chip.

— Upgrade to the A6 logic chip. Apple’s projections of nearly 300m iOS units for 2013 is such a sheer volume that "a seemingly benign metric like SoC die size for iPhone 5 [which is 95 mm2, 22% smaller than the A5] is actually meaningful enough to move the worldwide capex for semiconductor industry by 5% for every 10-sqmm variation," Kumar observes. He factors in 32nm capital intensity, Apple’s unit growth and die size, and determines that Apple’s chip partner Samsung could keep its logic capex spending flat in 2013 just to keep up with manufacturing the new A6 chips. (Apple also is using a dual-core ARM-A15 cores to run at 2× speed for the CPU, which Apple believes is better than Intel’s SoC core roadmap.

Barclays’ Muse points out that anything that means more 28/20nm chips means more litho-intensive processing, which "should benefit ASML disproportionally."

— More DRAM memory content, no extra NAND. DRAM content in the iPhone 5 is doubled to 1GB; Kumar actually had expected an increase in NAND content in the iPhone 5, but apparently Apple’s keeping it steady at 16-32-64GB, which underscores "the cautious commentary on wafer starts and capex from NAND companies," he writes. Among chip tool suppliers possibly affected, KLAC has higher exposure to logic/foundry and LRCX is more heavy into NAND than peers, but the extra DRAM content in the iPhone 5 likely makes up for that. Thus, the extra DRAM and no extra NAND means it’s "a wash" for suppliers.

— Upgraded to in-cell display technology. Putting touch sensors inside the panel, vs. adding a separate touch layer on top of the LCD panel, helps reduce the display’s thickness, which means the phone can be thinner or more features can be improved such as a bigger longer-life battery, explains Vinita Jakhanwal, director for small and medium displays at IHS iSuppli. LG, Sharp, and Japan Display are all potential suppliers of the in-cell display — if they can keep up with demand.

— Audio, antenna upgrades mean more sapphire. Sterne Agee’s Andrew Huang points to Cirrus Logic as a big beneficiary of a new "wideband audio" feature that can fill up more frequency spectrum to improve voice sound quality. Magnachip Semiconductor gets extra business tied to Cirrus Logic, points out Barclays’ Muse. Another winner is Corning, whose Gorilla Glass 2 is likely used as the cover glass for the iPhone 5, he says.

Huang also points out the iPhone 5’s increased used of sapphire, both as a camera lens cover and as the substrate (silicon-on-sapphire) for the antenna switch to automatically switch antenna connections, is a trend worth watching: "Within the next 12-18 months, we believe sapphire content per mobile phones could increase," he writes, suggesting eventually it might supplant the cover glass material. The silicon-on-sapphire trend likely benefits Rubicon (SoS wafer sapphire substrate supplier) and Peregrine Semiconductor (SoS switch component supplier). [Corrected 9/20: Soitec makes the actual SoS wafers for Peregrine.] "Our checks indicate that Rubicon supplies ~30-40% of the market for SoS wafers," he writes, and although a number of other ingot makers are currently getting qualified, "it is much more difficult to core, slice and polish SoS wafers, which suggests margins for SoS wafers are comparable, maybe even lower than those of LED wafers." Muse adds that Magnachip gets a foundry-biz boost from Peregrine, too.

September 14, 2012 – DAS Environmental Expert says it has a new system that offers a more environmentally friendly way to clean waste process gases produced in LED manufacturing.

LED demand continues to soar due to demand for backlighting (mobile devices and TVs) and general lighting — Yole Développement projects 2012 sales of $3.5B this year, doubling since 2010, and doubling again to $7B in 2014.

With that ramp-up, though, LED manufacturers have to deal with manufacturing process ramifications, such as the heavy use and disposal/emissions from process gases including ammonia and hydrogen. Taiwan is expected to enact stricter regulations in 2013 for waste water/gas disposal, which will emphasize the need for more environmentally friendly processes, notes DAS.

The company’s new LARCH system is said to be "based on a simple principle:" Initial thermal dissociation of ammonia is achieved by reaction heat; hydrogen is then ignited and burned off by electrical heating elements to be safely released into the atmosphere. (Heat generated by the reactions is transferred to a downstream heat exchanger.) It "economically" achieves low emission values, which means it can replace wet scrubbing processes that create large quantities of ammonia solution that must be further managed, the company explains.

The new LARCH system "has already generated a lot of interest" and enquiries from potential customers, according to Guy Davies, director of DAS’ gas treatment business unit. "Beyond LED manufacturing, DAS sees the system "finding application in other processes in which ammonia and hydrogen are generated." (DAS has other abatement systems targeting MOCVD technology but it’s unclear how or if they are related to LARCH.)



The LARCH system for processing and disposal of waste gases in LED manufacturing. (Source: DAS)

September 12, 2012 – Global demand for semiconductor manufacturing equipment slipped -4% in 2Q12 with softness in just about every region — except in Taiwan, which stepped on the pedal during the quarter, according to updated data from SEMI and SEAJ.

Worldwide semiconductor manufacturing equipment totaled $10.34B in 2Q12, down -4% from the previous quarter and about -13% from a year ago. Bookings were also down -4% sequentially, and were off by -10% year-on-year, to $9.70B. Note that these numbers include upwardly revised billings for North America, adding about $120M.

SEMI’s most recent predictions issued earlier this summer at SEMICON West indicated overall chip equipment demand would slip -2.6% in 2012 to $43.53B — and only that slight because the two biggest end-user regions, Korea ($11.48B, +32%) and Taiwan ($9.26B, +8.6%), are still pushing forward. All other regions are expected to reduce their equipment spending by – 15% to -29%. Observers at SEMICON West issued alarms for weak demand in 3Q12 but picking up some in 4Q12.

The latest numbers for 2Q12 support that scenario, at least partially. Taiwan’s demand for chip tools soared 83% in 2Q12 to $3.25B, leapfrogging the region back to the No.1 spot. Korea, meanwhile, slipped -22% Q/Q to $2.59B, a growth-rate decline roughly in line with all the other regions which are expected to be sluggish this year.

* North America was revised up, from 2.16
Figures may not add due to rounding.
(Source: SEMI/SEAJ)

September 11, 2012 – Taiwan’s two biggest semiconductor foundries saw sales jump in August, and business for the full third quarter is looking up as customers pull in some orders.

TSMC’s August sales were about NT $48.9 billion (US $1.63B), up about 2% from July but up 32% from a year ago. Through 2012 so far, TSMC’s sales are up about 16% from Jan-Aug 2011. The company says its entire 3Q11 sales will be "slightly higher" than its guidance of ~7% growth (NT$136-138B) it issued in July, citing primarily "pull-in of certain customers’ shipments and better-than-expected mask revenue."

Sales at UMC, meanwhile were also up about 2% month-on-month to NT $9.8B (roughly US $327.0M), nearly 20% higher than August 2011, and their highest since Dec. 2010. For the year so far, though (Jan-Aug.), UMC’s sales are off about 3% from last year’s pace. The company currently predicts "mild revenue growth" in 3Q12 with a "marginal" increase in both wafer shipments and ASPs. As with TSMC, industry watchers agree that customers are jockeying for an early ramp to the traditionally strong fall build-up for holiday electronics sales.

(Note that we’re no longer calling TSMC and UMC "the world’s top two foundries" anymore — that’s because GlobalFoundries passed UMC for No.2 in foundry sales earlier this year, and is expected to remain there.)