July 16, 2012 — 3D IC and stacked die semiconductor packaging configurations are often difficult to image with an acoustic microscope because the multiple internal surfaces send back abundant echoes and re-echoes from the ultrasound pulsed into the stack.
Now, Sonoscan introduced a simulator software, SonoSimulator, that enables stacked die makers to check nondestructively for delaminations between layers. SonoSimulator software is now a standard feature on the Gen6 C-SAM acoustic microscope.
The SonoSimulator determines optimal gate positions and other parameters with far less effort than is possible with the physical stacked parts alone. It also results in higher quality acoustic images.
Operators create a virtual die stack that matches the characteristics of the physical 3D IC or die stack to be inspected, including defects at specified layers. The virtual defects help determine the optimum placement of gates to image specific levels in the stack.
Imaging parameters are easily transferred to the Gen6 Sonolytics software for imaging the physical 3D IC or die stack.
Sonoscan reports that the simulation software reduces the imaging time for 3D ICs and stacked die packages, and allows less-experienced operators to do the inspection effectively.
Sonoscan is the leading developer and manufacturer of acoustic microscopes and sophisticated acoustic micro imaging systems, widely used for nondestructive analysis of defects in industrial products and semiconductor devices. Internet: www.sonoscan.com.
Deposition rate for high-quality SiO2 and SiNx improved with changes to the plasma-enhanced chemical vapor deposition (PECVD) hardware, which also reduces cleaning overhead. The latest generation of Cobra ICP source improves etch rate and feature control capability.
The tool’s robotic handler optimizes processes. Combined with the system’s control and software interface, this improves diagnostics, reliability and serviceability, the company reports.
The PlasmaPro 100 is configurable with process chambers as stand-alone modules or clusters. Users can access over 6,000 process recipes through Oxford Instruments.
Oxford Instruments specializes in the design, manufacture and support of high-tech tools and systems for industry research. Learn more at www.oxford-instruments.com.
The ITRS undergoes major revisions on odd-numbered years. 2012 being an even-numbered year, very little change occurred to the Overall Roadmap Technology Characteristics (ORTC). However, within the working groups, some updates were worth noting.
First, the changes to the ORTC, presented at the TechXPOT by Bob Doering. Of interest were changes focused directly or indirectly on 450mm. ITRS has moved the forecast production start date to 2015-2016. The definition of
July 12, 2012 — CEA-Leti co-located its research updates presentation with SEMICON West 2012 in San Francisco, CA, this week. After the talks on device architecture, 3D and 2.5 packaging interconnects, large-scale computing and power consumption, and more, CEA-Leti’s researchers joined Solid State Technology’s digital media editor Meredith Courtemanche to talk about their fields of interest.
Hughes Metras, VP of strategic partnerships in North America, presented on cost and energy consumption in large-scale computing, and what technical innovations will meet the industry’s needs. Energy efficiency must improve at the circuit, interconnect, and system level, he said.
Silicon photonics waveguides are one way to significantly increase bandwidth in semiconductors. CEA-Leti is migrating to a 300mm Si photonics line in its research work. Laurent Fulbert, Integrated Photonics Program Manager at CEA-Leti, presented on the question of low-cost/low-power computing architectures, and the answers available in photonics.
Maud Vinet, LETI FDSOI Manager, IBM Alliance, shared the benefits of fully depleted silicon on insulator (FDSOI) transistor architecture. The performance? Excellent parasitic capacitance resistance because of the smaller gate length than bulk CMOS. The energy efficiency? Back bias allows tuning of the devices’ threshold voltage to reduce wasted power. (We cover energy efficiency of new transistors/interconnects in more detail here.) The manufacturing parameters? Easier than a FinFET, Vinet says, as the majority of processes are the same as today’s semiconductor fab methods. The one challenge is potential silicon loss, because planar FDSOI uses thin Si films on the order of a few nanometers.
Mark Scannell and Denis Dutoit both lead 3D interconnect operations at CEA-Leti, with Scannell focused on manufacturing and Dutoit on design. Unfortunately, we did not have time to interview Scannell, though his research is summarized here. The interview below is with Dutoit. Leti has both a 200mm and 300mm line for wafer-level 3D packaging research. 2.5D passive interposers and 3D active stacks are “cousins” in device packaging, and you will see both of them used for different purposes for quite some time. While both 3D and 2.5D technologies can appear in the same package, the supply/value chains for each technology are quite different.
What’s in store in this area? “Smart” interposers are being developed with integrated passives on the interposer. 3D partitioning is enabling scaling as you like it — preventing chips from being held back to a larger device node by one of the blocks involved. Also on the horizon is via-last through silicon vias (TSV), an old technology that could now come back to offer continued TSV diameter scaling past what via-middle architectures can provide. The enabling technology here is permanent bonding. Also on CEA-Leti’s agenda is direct bonding, which spreads the stress gradient over the entire copper daisy chain, unlike today’s TSVs, and has a lower contact resistance. Finally, the researchers are considering sequential or monolithic 3D to make 50nm stacked structures on a wafer.
Before the meeting ended, Laurent Malier, CEO of Leti, spoke with Solid State Technology about the research organization’s current goals.
July 11, 2012 — Solid State Technology and SEMI announced the Best of West Award winner — Jordan Valley Semiconductor — during SEMICON West today. Jordan Valley Semiconductor’s QC-TT defect inspection system garnered the award for its ability to predict breakage in 450mm wafers, which are subject to more handling steps and more thermal stresses due to their larger size.
The award recognizes important product and technology developments in the microelectronics supply chain and is presented to a qualifying exhibitor at SEMICON West, the largest and most influential microelectronics exposition in North America. Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.
Jordan Valley Semiconductor’s QC-TT predicts damage on 450mm wafers in the semiconductor manufacturing environment, and can identify slip and other crystalline defects in wafers. These defects can contribute to lower yields.
Best of West is determined by a prestigious panel of judges representing a broad spectrum of the microelectronics industry.
SEMI is a global industry association serving the nano- and microelectronic manufacturing supply chains. For more information, visit http://www.semi.org.
PennWell Corporation is a diversified business-to-business media and information company that provides quality content and integrated marketing solutions for diverse industries, including Solid State Technologyfor the microelectronics manufacturing sector. Learn more at www.solid-state.com.
July 11, 2012 – PRNewswire – SEMICON West — International consortium SEMATECH qualified the GEMINI automated wafer bonding system from EV Group (EVG) through its systematic, rigorous Equipment Maturity Assessment (EMA) implemented within SEMATECH’s 3D Interconnect program and ISMI’s EMA team. The assessments of several tools are designed to determine equipment readiness for high-volume manufacturing (HVM) of 3D integration technologies. EVG
July 10, 2012 — While the packaging industry tends to focus on advanced packaging — processes at the wafer level, 3D integration, etc. — the bulk of semiconductor packaging falls under the
July 10, 2012 — Imec Technology Forum (ITF) took place just before SEMICON West 2012 opened in San Francisco, CA. ITF, held at the Marriott Marquis, focused on advanced semiconductor architectures and process technologies, with an additional impetus placed on the healthcare/medical industry.
Luc Van den hove, president and CEO, imec, spoke with Solid State Technology’s digital media editor, Meredith Courtemanche, covering imec’s major announcements and research presentations to take place during SEMICON West 2012. Summaries of imec’s presentations follow the video.
Logic
To enhance the advanced metal-high-k gate stack for next-generation logic devices, imec successfully demonstrated higher-k dielectric with Replacement Metal Gate (Metal-Gate-Last) transistors that achieved 200-1000x reduction in gate leakage relative to leading-edge logic devices in the industry with HfO2 high-k gate dielectric. To address the process control and scalability of the replacement metal gate for nano-scale devices, imec achieved tight electrical distribution down to 20nm gate length through detailed process optimizations. By providing fundamental insights into work-function influences due to metal intermixing in aggressively-scaled metal gates, imec’s research addresses an important source of variability in advanced transistors.
Imec has also invested significant effort in the development of 3D FinFET devices and high-k metal gate over the last 10 years. In the 14nm platform, these features will be combined with the next generation of stress engineering. For the next node — 10nm — we will replace the silicon channel in the FinFET devices with high-mobility materials. And for the nodes beyond 10nm, we are evaluating two possible device routes: tunnelFETs and junction-less nanowires.
Memory
In NAND Flash memory, imec further develops hybrid floating gate architecture, scaling this architecture to 15nm and beyond. Beyond 10nm, the main emerging technology is resistive RAM (RRAM). We’ve made significant progress on RRAM: imec recently announced 10nm functional RRAM, made significant improvements in performance and reliability of RRAM cells by process improvements and clever stack-engineering, and increased fundamental understanding of RRAM process technology.
In DRAM memory, imec is helping to scale MIMcap technology with a focus on materials. Beyond MIMcap, SST-MRAM is the leading candidate on the industry’s emerging DRAM roadmaps. Therefore, in November 2011, imec launched a program on SST-MRAM, for stand-alone DRAM as well as replacement of embedded SRAM.
Advanced lithography
To enable further scaling, imec is focusing on the extreme ultraviolet (EUV) lithography pre-production readiness and on extending immersion lithography using advanced patterning integration schemes. To further push the limits of 193nm immersion lithography and overcome some of the critical concerns for EUV lithography, imec implemented 300mm fab-compatible Directed Self-Assembly (DSA) process line all-under-one-roof in imec’s 300mm cleanroom fab. Imec’s DSA collaboration aims to address the critical hurdles to take DSA from the academic lab-scale environment into high-volume manufacturing.
Interconnects
The focus of imec’s nano-interconnect program is technology scaling including materials, process, integration, reliability and system aspects.
Imec is investigating half pitch (hp) multiple patterning techniques in combination with immersion lithography, and EUV lithography with single or double patterning techniques.
To improve the mechanical stability and low-damage patterning and integration schemes to reduce the k value, imec studies post-deposition techniques and the impact on performance and reliability.
To avoid wire resistance increase, imec explores metallization using new barrier and seed materials as well as novel deposition and filling techniques such as manganese and ruthenium based metallization, atomic layer deposition and chemical vapor deposition techniques.
3D integration
3D integration enables system scaling through 3D chip stacking with through-silicon-vias. Imec’s 3D integration processes are completely executed on 300mm. All processes and flows are tested on functional circuit demonstration vehicles. As part of the INSITE program, imec proposes flows for modeling, simulation, design and testing of 3D systems.
14nm, FinFETs
Imec’s early-version PDK (process development kit) for 14nm logic chips is the industry’s first to address the 14nm technology node. It targets the introduction of a number of new key technologies, such as FinFET technology and EUV lithography. With this PDK release, imec leads the way to an industry-standard 14nm PDK. In addition, the PDK anticipates the introduction of a number of new technologies at the 14nm node. The main example is the use of FinFET transistors, which have a larger drive per unit footprint and higher performance at low supply voltages compared to the traditional planar technologies. Evolutions of this PDK will gradually also introduce the use of high-mobility channel materials. The PDK includes elements of both immersion- and EUV lithography, opening the way for a gradual transition from 193nm immersion to EUV lithography.
Optical I/O
Future systems will become increasingly dependent on a high input/output bandwidth. Not only between systems, but also between the chips in a system, or even between the cores on a chip.
With optical components, it is possible to build interconnects that have the required bandwidth without consuming more power. Silicon photonics allows fabricating optical components with state-of-the-art semiconductor equipment, using the same processes and tools as for the fabrication of state-of-the-art chips.
At Semicon West, imec will announce the first important results of its industrial affiliation program (IIAP) on high-bandwidth optical input/output. This program is working towards a manufacturable solution for achieving high-bandwidth communication by modeling and engineering optical solutions for high-bandwidth communication between CMOS chips.
July 8, 2012 — Active-matrix organic light-emitting diode (AMOLED) displays have been deployed in small- and medium-size display applications since 2009, pushed by smartphone integration. While large-size AMOLED panels have been used in TVs since Sony’s 11” AMOLED TV debuted in 2008, they currently hold <0.1% market share, according to the new report, “AMOLED TV Development Trend and Competitiveness Analysis,” from Displaybank.
AMOLED TVs will target the LCD TV market by offering fast response time, higher color gamut, and better contrast ratio. However, AMOLED TVs do carry slightly higher production costs, at least in the initial period of mass production ramp-up, reports Displaybank.
Panel makers such as Samsung Mobile Display (SMD) and LG Display (LGD) will likely drive productivity and performance improvements to large-area AMOLED manufacturing technology. Areas for improvement include the thin-film transistors (TFT), deposition, encapsulation, and more. Materials costs may also fall when AMOLED ramps to higher volumes.
With higher production yields, large-size AMOLED display panels will improve cost competitiveness with LCDs. This will allow AMOLED TVs to lead in global TV growth, hitting 72 million units by 2020 and capturing more than 64% market share in the 45"+ global TV market.
“AMOLED TV Development Trend and Competitiveness Analysis” from Displaybank covers development status by major panel makers, analysis of the competitiveness of performance and process, a forecast of 55" AMOLED panel production costs and TV ASPs, a forecast of AMOLED TV and TV-use panel market (~2020), and a forecast of the overall AMOLED panel market by size/application(~2016). Learn more at http://www.displaybank.com/_eng/research/report_view.html?id=869&cate=
The award recognizes important product and technology developments in the microelectronics supply chain and is presented to a qualifying exhibitor at SEMICON West, the largest and most influential microelectronics exposition in North America.