Category Archives: Power Electronics

A UC Riverside-led research project is among the 32 named today by U.S. Energy Secretary Ernest Moniz as an Energy Frontier Research Centers (EFRCs), designed to accelerate the scientific breakthroughs needed to build a new 21st-century energy economy in the United States. “Spins and Heat in Nanoscale Electronic Systems” (SHINES) will receive $12 million over four years from the Department of Energy. The lead researcher is UC Riverside Professor of Physics Jing Shi, who will work with researchers from seven universities.

SHINES is one of 10 new projects announced today, along with 22 other projects receiving new funding based on achievements to date. The Department of Energy announced a total of $100 million in funding to support fundamental advances in energy production, storage, and use.

“Today we are mobilizing some of our most talented scientists to join forces and pursue the discoveries and breakthroughs that will lay the foundation for our nation’s energy future,” Secretary Moniz said. “The funding we’re announcing today will help fuel innovation.”

He said the intent of the Energy Frontier Research Centers is to make fundamental advances in solar energy, electrical energy storage, carbon capture and sequestration, materials and chemistry by design, biosciences, and extreme environments.

“I am happy to hear the news,” said Shi, the UCR physics professor who has put together an interdisciplinary team of  researchers from UC Riverside, UCLA, Johns Hopkins, Arizona State University, University of Texas, Austin and Colorado  State University, Fort Collins.

“I’m looking forward to seeing the scientific advances that they come up with,” said Michael Pazzani, UC Riverside’s Vice Chancellor for Research and Economic Development. “This is exactly the kind of scientific leadership that UC Riverside has been encouraging and supporting This project will lay the groundwork for energy technology for the nation.”

SHINES will investigate several aspects of basic research: new ultrathin films, nanostructured composites, high resolution imaging, the transport of electrical signals, heat and light. “All of it will be studied, modeled and simulated in order to help the nation’s ability to advance in the way we use energy,” said Shi, the lead researcher.

SEMI today reported the worldwide PV manufacturing equipment billings and bookings for the first quarter of 2014. Worldwide billings declined to $240 million in Q1 2014, a decrease of 42 percent from the prior quarter though just 6 percent below the same quarter a year ago. Worldwide bookings for the first quarter grew to $296 million, 18 percent above Q4 2013 and 44 percent higher than Q1 2013. At 1.24, the book-to-bill ratio broke above parity for the first time since 1Q 2011 with bookings at the highest quarterly value since Q1 2012.

PV bookings

On the regional basis, equipment sales were dominated by Asia. For the first quarter, Asia represented over 70 percent of total billings and over 80 percent of the total bookings.

The worldwide PV equipment billings and bookings data is gathered jointly by SEMI and the German Engineering Federation (VDMA) from about 40 global equipment companies that provide data on a quarterly basis.

The power supply/PFC segment will dominate the business from 2015-2018, ultimately representing 50 percent of device sales, according to a new Power GaN Market report from Yole Developpement. At that point, automotive will then catch-up.

“In UPS applications, the medium-power segment is likely to be very much in line with the GaN value proposition, and savings at system level will be demonstrated. We think GaN technology could grab up to 15 percent of market share in this field by 2020,” details Dr Philippe Roussel, Business Unit Manager, Compound Semi., LED, Power Electronics and Photovoltaics.

Screen Shot 2014-06-17 at 1.19.50 PM

Room for extra cost in motor drive applications is unlikely. Therefore, the incentives to implement new technologies such as GaN have to be serious and strong. Considering the possible improvement of conversion efficiency, and augmented by a predictable price parity with Si solutions by 2018, Yole Développement expects GaN to start being implemented at a slow rate in motor control by 2015-2016, and reach around $45M in revenue by 2020.

The PV inverters segment has already adopted SiC technology, and products are now commercially available. It’s possible that GaN could partially displace SiC thanks to better price positioning. However, now that SiC is in place, qualifying GaN may be more challenging.

Recent announcements show that the GaN industry is taking shape as mergers, acquisitions and license agreements are settled. ”The latest Transphorm-Fujitsu agreement, in addition to Furukawa’s IP portfolio’s exclusive licensing, are positive signs that GaN technology is spreading across the value chain, reinforcing the leaders’ market position but likely leaving the weakest players by the wayside,” comments Philippe.

Reasonably speaking, Yole Développement forecasts that 2014 will only generate $10M – $12M in device sales (in addition to R&D contracts and so forth). Such a moderate business means only the strongest will survive, and that several early-birds will see their cash-flow swiftly dissipate.

According to Yole Développement, the GaN business will really ramp up in 2016, exceeding the “psychological threshold” of $50M in revenue. How can GaN survive the next one to two years?

“At the risk of being overly-pessimistic, some companies will not survive, and will either be acquired or go bankrupt”, says Yole Développement.

By Mike Rosa, Applied Materials

In 2004/2005, shipments of 300mm wafer fab equipment (WFE) began to outpace that of 200mm platforms.  As the “baton” in the node-scaling race appeared to pass from 200mm to 300mm, it was clear that device manufacturers were transitioning to higher-volume, more cost-effective 300mm toolsets for cost efficiencies of the production of advanced memory and microprocessor devices.  Tool suppliers enabled the transition with the availability of the comprehensive 300mm toolset and began a new 300mm technology race, and leaving the major OEMs to focus on service and spares for the now legacy 200mm toolsets.  With advanced device designs fully transitioned to 300mm, many IDMs and foundries were left with growing excess capacity on their 200mm production lines.

Surprisingly, new life and attention has been refocused on the 200mm tool sets and available capacity as two phenomena are driving new requirement and economics.

First, in 2006, a MEMS (Micro-Electro-Mechanical Systems)-based accelerometer became a game changer when introduced into Nintendo’s next-generation Wii motion controller.  This was the first significant and novel use of a MEMS device for motion tracking in a high-volume consumer application.  Next, in 2007, when Apple Inc. first introduced the iPhone to the world, it came to light that MEMS devices were enabling a number of its advanced motion-based features.

Later, it would be noted that more than 75% of the semiconductor device content in the iPhone was sourced from 200mm wafer starts.  The devices manufactured on 200mm wafers spanned a wide variety of applications that included not only MEMS applications (motion, audio, RF, etc.) but also CIS (CMOS Image Sensor), communications, power management and analog devices.

Sold in the hundreds of millions per year, first the iPhone and then the multitude of other smart phones, tablet PCs, and related digital devices, that followed, drove the adoption of the emerging “More-than-Moore” class of devices (which were first pioneered  on 150mm wafers at the time) onto 200mm wafers.  These high-volume consumer applications gave rise to a resurgence in both new and used of 200mm equipment. This sudden requirement for new sourcing of “legacy” 200mm toolsets placed considerable strain on a supply  chain that then focused almost exclusively on 300mm; tool vendors struggled in  refurbishment, upgrade, and production of matching tools and processes that performed outside the requirements of traditional semiconductor applications (see Figure 1).

200mm equipment market gaiting new lease on life

200mm equipment market gaiting new lease on life

Some of these additional requirements — including new and thicker films (>20µm), advanced DRIE (Deep-Reactive-Ion-Etch) capabilities capable of delivering aspect ratios approaching 100:1, and new process capabilities like HFv (Hydrofluoric Acid vapor) release etch and Wafer Bonding — resulted in OEMs needing to restart 200mm tool development.  In some cases, OEMS needed to expand their product portfolios to support the growing needs of customers producing devices in the rapidly expanding “More-than-Moore” device segment.

Fast forward to 2014 —what a difference approximately seven years has made to the industry segment and more specifically the number of opportunities in the 200mm WFE market for the new class of devices.

The surge in mobile device applications and more recently wearable technologies, has meant that device manufacturers are increasingly  under  pressure to produce cheaper, smaller, more capable and more power efficient devices most economically and efficiently — and this remains optimally on legacy 200mm toolsets.  Combining this with the materials and production challenges presented by ultra-high volume applications spelled out in the ‘Trillion Sensor Vision’ and the now looming IoT (Internet-of-Things) (see Figure 2), and it becomes clear that OEMs who continue to support and develop solutions for the 200mm WFE market  have both significant challenges and potential rewards.

Figure 2. The IoT (Internet-of-Things) by most accounts prescribes device volumes as high as 1 Trillion (per year!) by 2024. These device volumes are accompanied by severe reductions in ASP. Maintaining expanded device functionality, a reduced device size and a further reduced cost of fabrication, presents considerable challenge to both device producers and tool OEMs alike.

Figure 2. The IoT (Internet-of-Things) by most accounts prescribes device volumes as high as 1 Trillion (per year!) by 2024. These device volumes are accompanied by severe reductions in ASP. Maintaining expanded device functionality, a reduced device size and a further reduced cost of fabrication, presents considerable challenge to both device producers and tool OEMs alike.

Rising to the challenge presented by the demands of these rapidly growing market segments, Applied Materials is an OEM that has, over the past several years, continued to invest in the R&D of its 200mm portfolio products.  Challenged to deliver new materials and processes (see Figure 3) in support the growing class of 200mm emerging technology applications that have come to include MEMS, CIS, Power Device, Analog, WLP (Wafer Level Packaging), TFB (Thin Film Battery), TSV (through-silicon via), etc., Applied Materials believes that working close to the customer and more collaboratively throughout the supply chain is paramount to success in a technically challenging and price sensitive market. The 200mm ecosystem supporting broadly expanding cost-senstive device classes represent a new fork in the roadmap that has been almost myopically focused on Moore’s Law evolution.

deliver substantially re-engineered 200mm toolsets to produce advanced materials and processes needed to support the next generation of “More-than-Moore” devices. Source: Applied Materials

deliver substantially re-engineered 200mm toolsets to produce advanced materials and processes needed to support the next generation of “More-than-Moore” devices. Source: Applied Materials

Learn more about how this dynamic market is changing at the session on “Secondary Equipment for Mobile & Diversified Applications” at SEMICON West 2014 in San Francisco, Calif on July 8-10.

By Debra Vogler, SEMI

The introduction of new materials, such as III-Vs, into high-volume manufacturing of semiconductors, likely will occur sometime around the 7nm and/or 5nm nodes. III-V’s introduction, along with the potential transition to 450mm wafers, and the increasing expansion of global regulatory requirements, will heighten environmental, health and safety (EHS) concerns that must be addressed as the industry goes forward. The Sustainable Manufacturing Forum to be held in conjunction with SEMICON West 2014, will feature experts in the manufacture of semiconductors, microelectronics, nanoelectronics, photovoltaics, and other high-tech products.

One of the Sustainable Manufacturing Forum speakers, Richard Hill, Technology Infrastructure manager at SEMATECH, will discuss how the addition of III-V materials into the high-volume manufacture of semiconductors will bring sustainability issues to the forefront, primarily driven by the toxicity of arsenic that is used in much greater quantities in III-V production. Challenges include wastewater treatment, toxic gas detection control and abatement, and the need for robust protocols to ensure operator and maintenance personnel safety. Hill will speak at the Next Generation Eco Fab session on July 9 at SEMICON West.

SEMATECH recently completed a joint study of III-V EHS challenges with the College of Nanoscale Science and Engineering (SUNY CNSE). The assessment consisted of running 300mm wafers through a representative 5nm III-V process flow (Figure 1). (Many semiconductor industry experts agree that III-V materials will enter the process flows in high volumes at 5nm.) Among the processes that will pose the greatest challenges with respect to III-V materials are MOCVD, CMP, wet etch/clean, dry etch, and film deposition. The project was heavily focused on understanding the levels of arsenic that would be present in wastewater, as well as loading of other III-V materials. The impact of III-V outgassing that could occur during processing and the amounts of gases that could be released when a tool is opened for maintenance were of particular interest in the project.

Figure 1. Example 5nm III-V flow: key ESH challenges. SOURCE: SEMATECH

Figure 1. Example 5nm III-V flow: key ESH challenges. SOURCE: SEMATECH

Among the high-level challenges associated with wet etch are the potential for arsine and phosphine outgassing (during processing).

“Wet etch tools are designed to have a controlled environment,” said Hill, “but they are not like high-vacuum systems that are designed to contain toxic gases.” Hill told SEMI that if the exhaust system fails during the processing of a wafer, it is critical to know the risks and ensure mitigation. The SEMATECH/CNSE project looked at a range of different chemistries and identified those that are low risk for arsine and phosphine generation (and therefore, a low risk of outgassing) and those that had a high risk of outgassing. The low risk chemistries are, naturally, the ones that the industry should try to design into a III-V flow.

The joint project also evaluated the III-V loading in wastewater from the wet etch process. “There were measurable quantities of arsenic in the waste stream,” said Hill. Though he added that while the levels weren’t significantly high, some treatment of the waste water would have to be done depending on what’s allowable within local discharge limits and permits. With the industry looking ahead to 5nm and already designing the fabs of the future, Hill believes that these results will be important for specifying wastewater treatment.

The joint SEMATECH/CNSE project also evaluated the wastewater stream from the burn wet scrubber when III-V materials are used in a contact etch (dry) process. The study found measurable arsenic in the wastewater. “Fabs of the future will need wet treatment facilities for arsenic and indium,” Hill told SEMI. “In recent years, concerns about indium have been elevated, and we believe that tighter restrictions on it will be introduced in the future.” Chamber clean is also critical when etching (dry) III-V materials. “If you don’t do the right type of cleaning regimen, you could have next-wafer contamination.” Additionally, without the proper protocol, maintenance personnel could be exposed to arsine or phosphine when the chamber is opened, depending on the process. The cleaning protocol is highly dependent on the type of etch being done, and each type could have different requirements.

For Hill, the key takeaway from the joint evaluation was that, while there are risks when processing III-V materials, there are no showstoppers — solutions can be engineered. “People should take these risks seriously, but they shouldn’t be scared off by them,” said Hill.

Sustainability and the Role of Collaboration and Standards

Steve Moffatt, CTO, Front-end Equipment at Applied Materials (also a speaker at the Next Generation Eco Fab session at the Sustainable Manufacturing Forum at SEMICON West), told SEMI that many established procedures for dealing with arsine and phosphine already exist. He views the efforts by the industry going forward as one of accurately quantifying the size and scope of the problem. “The methods are in place, but the absolute quantities of III-Vs will be substantially higher,” said Moffatt.

Additionally, other emissions (e.g., PFCs) that are well regulated and generally understood, will see an increase in the quantities as a result of more layers being processed for 3D chips. Even the potential transition to 450mm wafers will figure into the industry’s need for a more accurate scope of the EHS challenges involved. The increase in wafer size will naturally lead to larger manufacturing equipment noted Moffatt and that, in turn, will drive increases in energy, water, and process chemical consumption at both the tool and fab levels.

As regulatory pressure increases on a global scale, the situation also becomes more complex. Beyond the use of new materials such as III-Vs and nanomaterials, Moffatt commented that new methods of energetics (i.e., ways of putting energy into a processing system) will require very careful and close assessment of the risk control measures. Another sustainability issue arises from the basic fact that, as opposed to the highly prevalent element of silicon in the earth’s crust, many of the newer materials being used in higher quantities for semiconductor manufacturing (e.g.,Ga, As, etc.) are much less abundant. These exotic materials, of necessity, must be handled in the most efficient of ways.

Going forward, there will be increased regulatory pressure to reduce a fab’s carbon footprint and produce more sustainable products. Moffatt says the industry can expect more pressure to reduce greenhouse gas (GHG) emissions along with adhering to conflict minerals regulations and managing EHS concerns throughout the entire life-cycle of a product (Figure 2). “One company can’t do it on its own, it’s a life-cycle consideration,” said Moffatt. “If we have the right collaboration together, we have a greater probability with the right kinds of standards of bringing good, effective green chemistry solutions to high-value problems.”

Figure 2. Consensus building in multi-stakeholder life-cycle risk assessment of manufacturing technology and products. SOURCE: Applied Materials (used with permission of ITRS)

Figure 2. Consensus building in multi-stakeholder life-cycle risk assessment of manufacturing technology and products. SOURCE: Applied Materials (used with permission of ITRS)

Regarding standards activities on energetics, Moffatt pointed to ongoing collaboration and hazard assessment between SEMI, SEMATECH and other industry groups.

“We will need to continually evaluate the need for additional standards activities — both new and updates — in addition to industry collaboration on “Green” chemistry,” said Moffatt.  “As a starting point, sustainability concerns could be built into the initial assessment of new chemicals and processes, which will begin the discussion and raise awareness of these issues.”

Hill (SEMATECH) and Moffatt (Applied Materials) will be joined by speakers from IMEC, Intel, Samsung, Air Products, and MW Group at the “Next Generation Eco Fab” session of the Sustainable Manufacturing Forum at SEMICON West 2014, July 7-10 in San Francisco, Calif.  For more information, visit: http://www.semiconwest.org.

Dow Corning today established a higher industry standard for silicon carbide (SiC) crystal quality by introducing a product grading structure that specifies ground-breaking new tolerances on killer device defects, such as micropipe dislocations (MPD), threading screw dislocations (TSD) and basal plane dislocations (BPD). This groundbreaking new grading structure aims to optimize the range, performance and cost of next-generation power electronic device designs fabricated on Dow Corning’s high-quality Prime Grade portfolio of 100mm SiC wafers, which the company now offers in three new tiers of manufacturing-quality substrates labeled Prime Standard, Prime Select and Prime Ultra.

“Dow Corning recognizes that wide-bandgap semiconductor technology must deliver much more than high quality alone – it must deliver exceptional overall value,” said Gregg Zank, chief technology officer, Dow Corning. “Another Dow Corning industry first, our new SiC wafer grading structure meets this need head on. It is the direct result of our close collaboration with the globe’s leading power electronics device manufacturers, and aims to help give them what they need to quickly achieve their evolving design goals at an optimal price point.”

Each successive Prime Grade wafer tier under Dow Corning’s new product grading structure offers tighter tolerances for defect density and other critical performance properties that allow customers to precisely balance wafer quality and price, depending on the demands of their specific device applications. While many SiC substrate manufacturers promise low micropipe densities, Dow Corning is the first to specify low tolerances of other killer defects, such as TSD and BPD. Such defects reduce device yields, and inhibit the cost-efficient manufacture of large-area, next-generation power electronic devices with higher current ratings.

All 100-mm Prime Grade SiC wafers from Dow Corning offer consistently excellent mechanical characteristics to ensure compatibility with existing and developing device fabrication processes. The Prime Grade portfolio includes:

  • Prime Standard SiC wafers that guarantee MPD of 0.5 cm-2 or less, offering an attractive option for balancing performance and cost when designing simpler SiC power electronic components, such as Schottky or Junction Barrier Schottky diodes, with low to medium current ratings.
  • Prime Select SiC wafers that deliver more stringent tolerances for MPD (= 0.2 cm-2) and BPD (= 800 cm-2), making them suitable for more demanding SiC devices like pin diodes or switches.
  • Prime Ultra SiC wafers enable design of high-power devices that require the highest crystal quality. SiC substrates in this tier deliver extremely low MPD (= 0.1 cm-2), BPD (= 500 cm-2), TSD (= 300 cm-2) and a tightened wafer resistivity distribution for the design of today’s most advanced SiC power electronic devices. These include next-generation switching devices like metal-oxide-semiconductor field-effect transistors (MOSFETs), junction gate field-effect transistors (JFETs), insulated-gate bipolar transistors (IGBTs) and bipolar junction transistors (BJTs) or pin diodes. In addition, the superior substrate quality in this tier can benefit high-voltage (3.3 kV and higher) and high-current device designs.

“The precise tolerances defining each grade’s crystal quality coupled with Dow Corning’s highly competitive pricing structure reflect the company’s deep familiarity with the competitive demands of the silicon semiconductors market,” said Tang Yong Ang, vice president, Compound Semiconductor Solutions, Dow Corning. “Few competitors can bring Dow Corning’s legacy of technological excellence, application expertise and collaborative innovation in silicon materials, and apply it to the development of next-generation compound semiconductor technology. With the launch of this new wafer grading structure, we aim to provide SiC substrates that offer silicon-like quality and enable customers worldwide to compete and succeed in the fast-growing power electronics industry.”

Spending on RF power semiconductors for the wireless infrastructure markets has taken another jump in 2013. Other markets are seeing some moderation in growth as the global economic picture and political factors come into play but some sub-markets are showing a nice upside. Also, according to a new study from ABI Research, Gallium Nitride – long seen as the likely promising new “material of choice” for RF power semiconductors – is continuing its march to capture share, especially in wireless infrastructure.

“Gallium Nitride (GaN) is delivering increasing market share in 2014 and is forecast to be a significant force by 2019,” notes ABI Research Director Lance Wilson. “It bridges the gap between two older technologies, exhibiting the high-frequency performance of Gallium Arsenide combined with the power handling capabilities of Silicon LDMOS. It is now a mainstream technology which has achieved meaningful market share and in future will capture a significant part of the market.”

The vertical markets showing the strongest performance outside of wireless infrastructure in the RF power semiconductor business are the defense oriented segments, which Wilson describes as being now “a significant market” in total. Despite the poor press for defense oriented electronic hardware the actual performance in 2013 was better than originally thought for some sub-segments.

“RF Power Semiconductors” examines RF power semiconductor devices that have power outputs of greater than 4 watts and operate at frequencies of up to 3.8 GHz, which represent the bulk of applications in use today. The last study ABI Research published on this topic appeared late in 2013.

With the current release, analysis of the six main vertical segments (wireless infrastructure; military; industrial, scientific, and medical (ISM); broadcast; commercial avionics and air traffic control; and non-cellular communications) which was previously subdivided into 24 sub-segments, is expanded to 29 sub-segments.

Scaleo chip, the fabless semiconductor company in automotive electronics for powertrain, body control and driver-information, has used the GLOBALFOUNDRIES 55nm eFlash NVM Platform to develop a new family of microcontrollers.

GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology and a member of the Automotive Electronics Council (AEC), developed the optimized semiconductor manufacturing platform to specifically meet the stringent and evolving needs of the automotive industry.  Built on the company’s 55nm Low Power process and AEC-Q100 Group D qualified, the platform supports the implementation of non-volatile memory (NVM) in MCUs and SoC designs, as well as best-in-class, automotive grade SST-based embedded flash technology.

With a projected revenue growth of about 11 percent over the 2013-2016 period, automotive semiconductors are one of the fastest growing segments, with about twice the growth rate of the mobile device segment. The growing need for fuel-efficient, eco-friendly, safer and more connected cars is sustaining an increase of electronics content in vehicles. Powertrain applications are one of the fastest growing sub-segments and car manufacturers require more integrated, powerful and complex electronic systems to address both the stringent ISO 26262 functional safety standard along with mandatory reduction of emissions and fuel consumption.

“The growing need for advanced automotive electronics is driving semiconductor companies to strengthen their collaboration with foundry partners, so together we can act at all levels of the supply chain to provide the best products to our customers,” said Ana Hunter, vice president of product management at GLOBALFOUNDRIES. “The combination of Scaleo chip’s new microcontrollers and our 55nm automotive platform will improve the efficiency, performance, and power consumption of automotive ICs while maintaining adherence to the industry’s strict safety and quality standards.”

“Above and beyond the quality and efficiency of GLOBALFOUNDRIES’ technology and team, their long-term commitment to the automotive market, demonstrated by their current investment and roadmap, is a key foundation of our preference for the GLOBALFOUNDRIES 55nm eFlash NVM Platform,” said Bruno Paucard, President & CEO of Scaleo chip. “We see GLOBALFOUNDRIES as a critical partner for us, fully supporting the success of Scaleo chip and our products as well as the satisfaction of our customers.”

OLEA microcontroller silicon samples are already available for selected customers. Demonstration of the first plug-in, full hybrid demonstration car powered by OLEA microcontrollers will be available shortly.

Synopsys, Inc. today announced it has extended its collaboration with STMicroelectronics to include Samsung Electronics, enabling broader market adoption of ST’s 28nm FD-SOI technology for SoC design. Synopsys’ Galaxy Design Platform is production-proven on multiple designs based on ST’s 28nm FD-SOI technology. This collaboration extends the Galaxy design flow to Samsung in support of their strategic agreement to offer dual sourcing of ST’s 28nm FD-SOI technology. Developed over a multiyear collaboration with ST, the design flow enables concurrent area, power and timing optimizations to enable engineers to optimize their designs for the ST 28nm FD-SOI process.

“The close collaboration between ST design teams and Synopsys led to advanced silicon-proven design enablement solutions that fully leverage the performance and power promise of FD-SOI technology and provide the foundation needed to meet tight time to market windows,” said Philippe Magarshack, executive vice president, Design Enablement and Services, STMicroelectronics. “Our close collaboration with Synopsys has already enabled many successful tapeouts with mutual customers using Synopsys’ Galaxy Design Platform and Lynx Design System.”

The Synopsys design flow for ST’s 28nm FD-SOI is compatible with the Lynx Design System, a full-chip design environment providing innovative automation and visualization capabilities that enable higher designer productivity and faster design closure. A technology plug-in using ST’s 28nm FD-SOI Process Design Kit (PDK), standard cells and memories, adapts the production-proven Galaxy Design Platform-based RTL-to-GDSII flow for 28nm FD-SOI SoC designs, accelerating project setup and execution. Lynx automation simplifies and accelerates many critical implementation and validation tasks, including back-bias management across the flow, special connection checks, In-Design physical verification for well connections and UPF supply set management for N-wells and P-wells.

Galaxy advanced design enablement features like the IC Compiler tool’s concurrent clock and data optimization, layer-aware optimization, physical datapath and comprehensive support for hierarchical and low power design features can also be directly accessed by Lynx users for high-performance and low power CPU and GPU design.

“28nm FD-SOI is an ideal solution for customers looking for extra performance and power efficiency at the 28nm node without having to migrate to 20nm,” said Dr. Shawn Han, vice president of foundry marketing, Samsung Electronics. “Our close collaboration with Synopsys and ST will enable designers to reduce risk, accelerate time-to-market, minimize power and maximize performance to expand 28nm FD-SOI adoption.”

“Because the Galaxy Design Platform is silicon-proven on ST’s 28nm FD-SOI process with multiple tapeouts of low power designs running in the gigahertz frequency range, customers can adopt this technology with confidence,” said Antun Domic, executive vice president and general manager, Design Group at Synopsys. “Combined with the Lynx Design System and DesignWare IP, the Galaxy Design Platform enables engineers to derive maximum benefit from the FD-SOI process and our continued collaboration with ST and Samsung will ensure ease of adoption of FD-SOI for SoC design.”

After two years of decline, fab equipment spending for Front End facilities in 2014 is expected to increase 24 percent in 2014 (US$35.7 billion) and about 11 percent (US$39.5 billion).  In terms of equipment spending, 2015 may reach or even surpass historic record year 2011 (about US$39.8 billion). For the May 2014 SEMI World Fab Forecast publication, SEMI tracked more than 200 major projects involving equipment spending for new equipment or upgrades, as well as projects to build new facilities or refurbish existing facilities.   In the last three months, 265 updates were made to the database. See Figure 1.

Figure 1

Figure 1

In 2014, the three largest regions for fab equipment spending will be Taiwan with over US$10.3 billion, the Americas with over US$6.8 billion, and Korea with over US$6.3 billion.  In 2015, these same regions will lead in spending: Taiwan will spend over US$11 billion, Korea over US$8 billion, and the Americas almost US$7 billion. Although in sixth in regional equipment spending this year, the Europe/Mideast region will show the strongest rate of growth, about 79 percent compared to the previous year.  The same region will continue to grow fast in 2015, with an increase of about 20 percent.

Worldwide installed capacity is very low for both 2014 and 2015 and the SEMI data does not suggest that this will change over the next four years. Because of the increased complexity of leading-edge nodes, such as more process steps and multiple patterning, fabs experience a decline in capacity as the same fab space produces less.  Worldwide, installed capacity grew by less than 2 percent in 2013 and is expected to grow just 2.5 percent in 2014 and 3 percent in 2015.

SEMI’s detailed data predict that Foundry capacity continues to grow at 8-10 percent yearly (a steady pace since 2012) and Flash is up 3 to 4 percent for 2014. Although DRAM equipment spending is expected to grow by 40 percent in 2014 as many fabs upgrade to a leading-edge process, installed capacity for DRAM is expected to stay flat or even drop 2 percent.  SEMI’s reports also cover capacity changes for other product segments:  MPU, Logic, Analog/Mixed signal, Power, Discretes, MEMS, and LED and Opto.

The SEMI World Fab Forecast uses a bottom-up approach methodology, providing high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab. Additionally, the database provides forecasts for the next 18 months by quarter. These tools are invaluable for understanding how the semiconductor manufacturing will look in 2014 and 2015, and learning more about capex for construction projects, fab equipping, technology levels, and products.

The SEMI Worldwide Semiconductor Equipment Market Subscription (WWSEMS) data tracks only new equipment for fabs and test and assembly and packaging houses.  The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, or in-house equipment.