Category Archives: Chemical Mechanical Planarization

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Cabot Microelectronics Corporation (Nasdaq: CCMP), a supplier of chemical mechanical planarization (CMP) polishing slurries and a growing CMP pad supplier to the semiconductor industry, announced the appointment of Thomas F. Kelly, Vice President, Corporate Development, which is effective as of September 6, 2016. Mr. Kelly rejoins Cabot Microelectronics after serving as the Director of Global Raw Materials Procurement for Celanese Corporation from 2012 through 2016, and prior to that as the Vice President of New Business Development and the Program Management Organization of Chemtura Corporation, where he was employed from 2008 until 2012. He was employed by Cabot Microelectronics from 1999 through 2008, serving in various senior business operations, product management, and supply chain assurance roles.

“I am delighted to welcome Tom Kelly back to Cabot Microelectronics, and am confident his executive expertise from various global companies in the larger engineered materials and chemicals industries will benefit our company greatly in a number of important areas,” said David H. Li, Cabot Microelectronics’ President and Chief Executive Officer. “Tom knows our business, industry, customers and supply chain well, along with having developed important experience in mergers and acquisitions, business development, and corporate strategy from his more recent roles in helping to lead multi-billion dollar global businesses.”

In addition to this, the Company announced that as of September 1, 2016, Daniel J. Pike has resigned from his position as Vice President, Corporate Development, and will continue to serve the Company in a non-executive transition role until March 1, 2017. Mr. Li stated, “I would like to thank Dan for his significant contribution to the founding and growth of Cabot Microelectronics during his many years of service. All of us wish him well in his future endeavors.”

A novel SACVD PMD invention sets the benchmark for helium reduction efforts by achieving four key objectives: cost reduction, quality, process robustness and productivity.

BY JAE HEE KIM, Thin Film Dielectric Fabrication Engineering, Texas Instruments, Dallas, TX

The United States is the world’s largest helium supplier and half of its supply comes from a helium reserve regulated by the Bureau of Land Management just outside of Amarillo, Texas. As many predict, at the current rate of production the maximum expected life of this reserve is 2020. As a result of a shortage that began in 2013, the cost of bulk helium has been increasing significantly (FIGURE 1).

Helium 1

Considering semiconductor manufacturing is one of largest helium consuming industries [2], it becomes crucial to invest continuous efforts to minimize helium usage during wafer fabrication processes and to identify new opportunities for helium reduction. In this article, we’ll take a look at a new innovative process to do just that.

Sub-Atmospheric Chemical Vapor Deposition (SACVD) for pre-metal layer consumes a significant amount of helium to assist in process gas delivery during deposition and in-situ chamber clean which makes the best candidate for helium reduction effort benchmarking. Also, SACVD Pre-Metal Dielectric (PMD) consists of various processes including phosphosilicate glass (PSG) and borophospho-silicate glass (BPSG) which makes the fan-out process more applicable for a bigger impact on helium reduction. So how do we do it?

Objectives

There are four key objectives to a new SACVD PMD process development that my team has looked at: cost, quality, process robustness, and productivity. First, a new carrier gas was identified to maximize helium usage reduction. Second, solutions to both new hardware and process conditions were developed for quality improvement. A new blocker plate was qualified to improve within wafer thickness uniformity. Additionally, gas conditions were developed to improve the gap-fill capability for leakage reduction. Third, a new pressure condition was qualified for process robustness improvement. An old two-step baseline process was designed for better gap fill by depos- iting initial 4kA film at 700Torr for lower deposition rate and the rest of the film at BKM pressure, 200Torr for better cycle time. However, this baseline two-step process, which operates at near atmospheric pressure on a sub-atmospheric CVD tool platform, is marginal for pumping speed degradation which leads to inline defect. Susceptibility of defect formation was reduced by lowering process pressure from 700Torr to 600Torr during the initial PMD layer. Last, overall process conditions were evaluated to achieve a desirable deposition rate in order to ensure comparable manufacturing throughput. Furthermore, a new process condition was selected to avoid process chamber restriction for flexibility of manufacturing.

New process carrier gas identification

Initial process development was divided into two categories: BPSG and PSG. Development began with PSG since there is one less process parameter, Boron compared to BPSG process. Preliminary tests showed that a 100 percent N2 carrier drives an unstable film thickness range. Based on findings, a helium and nitrogen mix carrier gas was selected for further process evaluation. The main focus at this stage of evaluation were to identify process conditions including a helium and nitrogen mix carrier gas flow to achieve maximum helium savings, comparable cycle time, and thickness uniformity improvement.

Process condition development

Based on design of experiments (DOE) with four key process parameters (N2, He, O3, spacing), we learned that deposition rate is faster with increasing He and slower with increasing N2 and O3. Thickness uniformity degrades with total carrier gas flow. Based on DOE results, initial proposed condition was carrier 5500sccm (3:1 = N2:He), O3 3000sccm, spacing 200mils for better thickness uniformity and shorter cycle time while saving the maximum amount of helium.

Unfortunately, this condition degraded at baseline margin to form voids in 700Torr deposition film due to faster deposition rate. Focus was then shifted to identify a recipe condition that lowers the deposition rate during 700Torr deposition for a better gap fill capability which also can be used for both 200Torr PSG and two-step PSG to ensure manufacturing flexibility.

Based on deposition rate DOE with three parameters including Ozone, tetraethyl orthosilicate (TEOS) and spacing (TABLE 1), ozone flow has first-order effects on the deposition rate, and spacing has second-order effects. TEOS flow has third-order effects on deposition rates but also reduces dopant concentration of film. Temperature change was not considered since it affects other recipe conditions at a greater degree. Increasing pressure was also not considered since the process already operates at a high pressure of 700Torr.

Helium Table 1

Then it was decided to include Ozone and spacing, in addition to helium and nitrogen, into further process characterization. We ran comprehensive three factorial DOE to deposit 4kA PSG film at 700Torr at various settings of total carrier flow, spacing, and ozone. This was in order to achieve a lower deposition rate for better gap fill and good thickness uniformity. DOE conditions were determined based on JMP prediction profiler and calculators to evaluate a wide spectrum of different deposition rates at 700Torr and thickness range.

To evaluate the DOE result, two techniques were used. First, wafer samples were prepared by sputtering top down until they reached the very initial layer of PMD to open up any voids that are present in PSG film. Effectiveness of gap-fill capability was rated by quantifying a number of voids on the scanning electron microscopy (SEM) images captured at same magnification on the consistent location of the wafer sample. This is a more effective technique than collecting transmission electron microscopy (TEM) on a defined location on samples since top down SEM can capture broader areas of wafer samples. Second, wafers were also submitted for dynamic secondary ion mass spectrometry (SIMS) to ensure if the dopant profile throughout PSG film is comparable to the baseline. This critical step is to verify that there is no sign of unstable dopant distribution that could lead to any adverse effects, such as increased etch selectivity or poor gettering (FIGURE 2).

Helium 2

Based on DSIMS collected, it was found that the dopant concentration profile becomes unstable if the total carrier gas flow is less than 5500sccm. Phosphorous (P) concentration profile shows fluctuation all throughout the film at a total carrier gas flow less than 5500sccm while phosphorous percent profile was steady at total carrier gas at 5500sccm or higher (FIGURE 3).

Helium 3

Among many conditions that satisfy a total carrier gas flow of less than 5500sccm, when ozone flow is 5000sccm and total carrier gas is 5500sccm with a 3:1 ratio of nitrogen to helium, the top down SEM result shows a greatly reduced number of voids in film. This means the deposition rate during 700Torr is slow enough to improve gap-fill capability. At the same time, Ozone flow at 5000sccm was fast enough during 200Torr to maintain a comparable cycle time. Therefore, this condition can be used for both single step PSG and two-step PSG which allows flexibility for manufacturing to run both processes without equipment restriction. Dynamic SIMS also verified that this condition provided a stable dopant profile. Thickness uniformity was also comparable to the baseline on this recipe condition. Therefore, spacing 200mils, ozone 5000sccm, and a total carrier flow 5500sccm was chosen as a finalized new PSG condition.

For the BPSG process, the same technique was used for evaluation. DSIMS was used to ensure both Boron and phosphorous concentration profiles are comparable. The same carrier gas conditions with nitrogen and helium at a ratio of 3:1 of 5500sccm and Ozone 5000sccm were selected for the final condition. TEOS was increased from 600mgm to 800mgm to make sure the deposition rate is comparable to maintain manufacturing cycle time at PMD (TABLE 2).

Helium Table 2

Flash parametric legacy issue improvement

A high aspect ratio of device structure can cause voids in PMD that lead to poor isolation and yield loss. There are many contributing factors that modulate PMD voids, including a stacked gate vertical profile and a sidewall spacer profile. Among all contributing factors, however, a void-free PMD process was proven to be the most effective way to minimize leakage. The void-free PMD was achieved by qualifying a new two-step PSG process with a mix carrier gas.

The new two-step PSG process with a mix carrier greatly lowers the deposition rate during the initial PMD layer. This helps deposit film more uniformly at higher pressures to minimize voids, while depositing the rest of the PMD at a faster deposition rate at lower pressure helps to compensate cycle time loss from the initial deposition.

The new two-step PSG alleviates leakage susceptibility on the wafer edge and reduces sensitivity to the PMD void-contributing factors by adding significant margins to leakage failure due to voids. Notably, the PMD gap-fill improvement added significant integration marginality between the sidewall spacer profile and the PMD which led to lower process and tool sensitivity at the sidewall spacer etch. This increases manufacturing capacity by releasing sidewall spacer etch process chambers with historical leakage failure susceptibility to production. Most importantly, parametric outlier probability was greatly improved by 20 percent and a zero standard parametric failure rate was achieved by qualifying void-free PMD (FIGURE 4).

FIGURE 4. Void-free PMD (right) shows excellent gap fill while baseline PMD (left) shows a void filled with W [3].

FIGURE 4. Void-free PMD (right) shows excellent gap fill while baseline PMD (left) shows a void filled with W [3].

Process robustness improvement

There were technical challenges with center cluster defects on the new two-step process. Center cluster defects affected isolation contact resistance. Based on TEM (FIGURE 5), defects formed around where a low deposition rate completed and a faster deposition rate resumed. Dynamic SIMS showed a phosphorous concen- tration peak at the defect which explained why this defect had a high contact etch selectivity.

Helium 5

After exposing the test wafer for 24 hours at atmosphere, haze was formed on its substrate. Time of flight secondary ion mass spectroscopy showed that haze was caused by a reaction between excessive phosphorous and atmospheric moisture. Additionally, a repeatability test showed that the tail of cluster defects extended towards gas exhaust. Based on these findings, this baseline two-step process which operates at near-atmospheric pressure on a sub-atmospheric CVD tool platform is marginal to maintain sufficient pumping speed during pressure transition from high process pressure to low process pressure (FIGURE 6). This significantly increased the chances of forming center cluster defects with a heavier carrier gas. This is because the pumping speed is lower at a higher pressure and mean residence time is longer at a higher pressure. Additionally, conductance is lower with N2 than with He due to heavier molecular weight.

Helium 6

In order to address this issue, the new two-step process was reevaluated and a new process condition was developed. As summarized in TABLE 3, it was decided to maintain the same carrier gas flow to maintain bulk helium savings. Pressure condition for the first deposition step was modified from 700Torr to 600Torr. This new two-step process improved robustness by reducing risks of pumping speed degra- dation during the pressure transition from 600Torr to 200Torr. The new two-step process is also able to deliver a strong PMD void-fill improvement by maintaining a zero parametric failure rate for leakage.

Helium Table 3

Thickness uniformity improvement

The new SACVD PMD invention took part not only in process development but also in hardware improvement. The new process with a baseline helium blocker plate that helps uniform process gases dispersion showed higher within wafer thickness range which appeared on wafer substrate as in forms of lightly discolored spots. Based on Energy Disperse Spectroscopy (EDS) and Dynamic SIMS, defects were a part of the top 270A of PSG film. The location of spots were nicely matched to the hole pattern of the helium blocker plate. The nitrogen blocker plate was qualified as it consisted of the same material as the helium blocker plate but had a more dense hole pattern. It was not only able to eradicate the anomaly on the surface film but also to alleviate the baseline starburst pattern on the deposited film.

DSIMS confirmed that the dopant profiles on the nitrogen blocker plates are comparable to the ones on the helium blocker plate. The nitrogen blocker plate improved within wafer thickness uniformity by 35 percent on a new PSG film ranging from 12kA to 16kA compared to an old PMD baseline performance (FIGURE 7). Consequently, this improved the process capability index at post PMD Chemical Mechanical Polish (CMP) by improving process targeting based on improved thickness uniformity.

Helium 7

Manufacturing and engineering productivity increased, as well, due to reduced tool down time. New blocker plate qualification also alleviated the sensitivity of film thickness uniformity to the heater age and possibly helped to extend heater life on the PSG chambers and reduce tool down time for range failure.

Conclusion

This novel SACVD PMD invention successfully set the benchmark for helium reduction efforts by achieving four key objectives: cost reduction, quality, process robustness, and productivity. It brings a substantial impact on bulk helium gas savings with worldwide limited supplies and increasing demand. The new PMD reduces bulk helium usage by 80.4 percent and 77.1 percent for PSG and BPSG respectively during deposition and completely eliminates helium usage during in-situ chamber clean.

This new process achieved outstanding gap-fill capability by lowering the deposition rate at initial PMD layer. The process successfully eliminated leakage failure at parametric by adding significant process integration marginality for void formation. It also improves process robustness by reducing risks of pumping speed degra- dation during the pressure transition from 600Torr to 200Torr. Process conditions are carefully developed for comparable manufacturing throughput and harmonized between single step PSG and two-step PSG in order to ensure manufacturing flexibility. Lastly, new hardware qualification also helps improve quality and productivity by lowering within wafer thickness range.

References

[1] C. Kaneshige, 2013, an excerpt from GE Healthcare published in 2012
[2] Semiconductor Industry Association, August 1, 2012, Hearing on “Helium: Supply Shortages Impacting our Economy, National Defense and Manufacturing” (Hearing held on July 10, 2012). Testimony for the Record of the Semiconductor Industry Association.
[3] D. Rodriguez, 2014, unpublished

Nova Measuring Instruments, a provider of metrology solutions for advanced process control used in semiconductor manufacturing, announced today that a leading foundry recently selected Nova’s optical and X-ray metrology solutions for multiple process steps, including CMP, Etch and Deposition, for its most advanced technology nodes. The selection by this major foundry in Asia covers metrology solutions for process control in production in 10nm and 7nm technology nodes and metrology solutions for R&D process development in 5nm technology node. As part of this selection, Nova has already started to deliver integrated and stand-alone platforms during the fourth quarter of 2015 and will continue to support the ramp up for these advanced technology nodes during the coming years.

Nova’s solutions were selected due to superior metrology performance, high productivity and technology extendibility, to handle the future challenges of critical dimension (CD) and materials measurements of 3D FinFET gates in sub 10nm technology nodes. The selection was made following an intensive evaluation and includes Nova’s most advanced product suite of integrated and stand-alone metrology systems, offering unique and advanced measurement capabilities, enhanced with NovaMARS innovative modeling software. Nova’s comprehensive solution demonstrated best-in-class technology offering, combined with enhanced productivity capabilities and long term extendibility.

“This selection by the world’s leading foundry, following a comprehensive evaluation, represents a powerful vote of confidence in our metrology portfolio for the most advanced technology nodes,” stated Eitan Oppenhaim, Nova’s President and CEO. “This selection is another proof point for our industry leadership, as well as our strong position in the foundry segment, and validates our expectations for extensive growth in metrology intensity in the advanced nodes. I am gratified that we were able to demonstrate, once again, the value of our disruptive innovation, which matches aggressively to our customer’s roadmap and provides a great support for our growth plans in the coming years.”

Oppenhaim concluded, “We are reaffirming our revenue guidance for the fourth quarter of the year, representing record top-line results in 2015.”

The company revenue guidance for the fourth quarter of 2015 is $37 million to $41 million, which implies to $145.5 million to $149.5 million in annual revenues in 2015.

Entegris, Inc., a developer of yield-enhancing materials and solutions, today announced new post-chemical mechanical planarization (post-CMP) cleaning solutions for semiconductor manufacturing. The new PlanarClean AG family of products were designed for use in 10nm processes and below, and add to Entegris’ portfolio of post-CMP cleaning solutions.

“Entegris has been the industry leader in post-CMP cleaning for many years. Our PlanarClean family products have been widely used in wafer fabs around the world. To address greater complexity of wafer production at the leading-edge nodes due to the addition of many new materials, such as cobalt and tungsten, we carefully re-formulated our PlanarClean solution to provide superior cleaning without damaging advanced films or new materials,” said Cuong Tran, director of post-CMP cleans for Entegris. “PlanarClean AG meets the needs for advanced processes, while also conforming to new safety guidelines outlined by our customers.”

The CMP process in silicon wafer production consists of a mechanical polishing step which utilizes a chemical slurry formulation to remove unwanted conductive or dielectric materials from the surface of the integrated device, achieving a flat and smooth surface upon which additional layers of integrated circuitry are built. The post-CMP cleaning step removes nanoparticles to minimize potential wafer defects while maintaining the integrity of the layers of materials already in place.

Changes to the number and types of films and materials exposed during cleaning in advanced processes have highlighted a need for specifically formulated cleans. In addition, changes to the particles used in slurries have rendered many of the traditional post-CMP cleaners ineffective and inefficient for leading-edge technologies, specifically in Front-End-of-Line (FEOL) processes. These challenges are now pushing semiconductor manufacturers to consider formulated cleans over commodity cleans.

PlanarClean AG formulated solutions meet these needs by providing one-step, superior cleaning in advanced processes that include copper, cobalt and tungsten, while protecting the underlying thin films and materials. Its proprietary formulation offers increased performance through enhanced reliability and yield, low to zero corrosion and defects and increased queue time. In addition, PlanarClean AG provides a cost-of-ownership advantage by reducing the amount of chemistry required in the cleaning step, and meets the latest EHS safety requirements for fab chemistries. The products have been successfully evaluated in multiple leading-edge fabs and are currently available to all customers.

 

Chemical mechanical planarization (CMP) is a critical process technology step in the semiconductor wafer fabrication process. In this process step, the top surface of the wafer is polished or planarized to create a flat surface.

The CMP tool is comprised a rotating platen, slurry, pad, holding ring, brush, and pad conditioner. The mechanical element of this system applies downward pressure to a wafer surface, while the chemical reaction increases the material removal rate. The value chain of the CMP market consists of different players, including semiconductor material suppliers, CMP integrated solution providers, semiconductor wafer suppliers, semiconductor device manufacturers, slurry & pad manufacturers, technology solution providers, and CMP equipment manufacturers.

While CMP is still used for its traditional polishing applications for interlayer dielectrics, it’s also finding employment in more advanced applications, such as bulk oxide polishing, shallow trench isolation, “stop on poly” isolation, and polishing of various dielectrics in advanced transistor designs.

According to a recent market research report published by MarketsandMarkets, the global CMP market is expected to reach $4.94 Billion by 2020, at an estimated CAGR of 6.83% from 2015 to 2020.

Though the CMP market is at the mature stage, it still continues to evolve depending on the end users. The industry is being forced to adopt much innovation in process technologies and applications; as a result, different CMP processes have been evolved with technology nodes and newer applications such as MEMS, advanced packaging, and advanced substrates.

Applied Materials, Inc. (U.S.) and Ebara Corporation (Japan) are the major CMP equipment suppliers. Phoenix-based Entrepix offers unique CMP foundry services.

CMP includes consumable products, polishing pads and slurries. This CMP consumables market is dominated by major market players such as Cabot Microelectronics Corporation (U.S.), Fujimi Incorporated (Japan), and Dow Electronic Materials (U.S.).

Success in CMP lies in optimizing the many process variables. In addition to wafer variables such as film type and pattern density, CMP variables include: time, pressure (force applied to the wafer and pad), velocity, temperature, slurry feed rate, polishing motion, slurry chemistry and pH potential, slurry particle size, pad elasticity, pad hardness and pad condition method. An optimized CMP process also depends on removal rates of the film being planarized, adhesion stability of the film, minimal defects such as scratchs or pits, minimal corrosion (in the case of Cu), and the adhesion of organic or inorganic surface residues formed during the CMP process.

With alternate channel materials on the horizon for future logic transistor, III-V materials such as gallium-arsenide (GaAs), gallium-indium-phosphide (GaInP), and indium-phosphide (InP) are now in R&D which leads to questions regarding direct process costs as well as indirect EHS costs. Much of the concern involves the possible reaction and release of toxic hydrides such as arsine, and phosphine. SEMATECH worked with imec to monitor hydrides produced during CMP processes for high-mobility compound semiconductors.

Suggested Additional Reading:

Chemical Mechanical Planarization: Historical Review and Future Direction

Northern California Chapter of American Vacuum Society: CMP Users Group

CMP Technology Evolving to Engineer Surfaces

Reduced defectivity and cost of ownership of copper CMP cleans

Safe CMP slurries for future IC materials

The rule of three

According to a new market research report on the “Chemical Mechanical Planarization Marketby type (Equipment & consumables), Application(IC manufacturing, MEMS & NEM, Optics and Others), Technology (Leading edge, More Than Moore’s, and Emerging), and Geography (North America, Europe, APAC and RoW) – Global Forecast to 2020”, published by MarketsandMarkets, the market is expected to grow at a CAGR of 6.83% between 2015 and 2020, and reach $4.94 Billion by 2020.

Chemical mechanical planarization is a critical process technology step in the semiconductor wafer fabrication process. In this process step, the top surface of the wafer is polished or planarized to create a flawless flat surface that is essential to make faster and more powerful semiconductor devices with the aid of chemical slurry & mechanical movements. The CMP tool is comprised a rotating platen, slurry, pad, holding ring, brush, and pad conditioner. The mechanical element of this system applies downward pressure to a wafer surface, while the chemical reaction increases the material removal rate. The value chain of the CMP market consists of different players, including semiconductor material suppliers, CMP integrated solution providers, semiconductor wafer suppliers, semiconductor device manufacturers, slurry & pad manufacturers, technology solution providers, and CMP equipment manufacturers.

The global Chemical Mechanical Planarization Market was worth USD 3.32 Billion in 2014, and it is expected to reach USD 4.94 Billion by 2020, at an estimated CAGR of 6.83% from 2015 to 2020. Though the CMP market is at the mature stage, it still continues to evolve depending on the end users. The industry is being forced to adopt much innovation in process technologies and applications; as a result, different CMP processes have been evolved with technology nodes and newer applications such as MEMS, advanced packaging, and advanced substrates. The growing demand for consumer electronic products, increasing need of wafer planarization, and increasing use of micro-electro-mechanical systems (MEMS) is driving the global CMP market.

The CMP equipment market is expected to grow at the highest CAGR of 8.32% from 2015 to 2020. The key factors behind the high growth of the CMP equipment market is the strong growth in semiconductor equipment and capital spending. The CMP consumables market was valued at USD 2.25 Billion in 2014 and is expected to reach to USD 3.21 billion by 2020. The Applied Materials, Inc. (U.S.) and Ebara Corporation (Japan) are the major CMP equipment suppliers for different integrated device manufacturers.

This CMP consumables market is dominated by major market players such as Cabot Microelectronics Corporation (U.S.), Fujimi Incorporated (Japan), and Dow Electronic Materials (U.S.).The CMP regional market is mainly dominated by Asia-Pacific, followed by North America and Europe. The Asia-Pacific region accounted for the largest market share of ~67% and is expected to grow at the highest CAGR of 7.40% during the forecast period, followed by North America. The countries in Asia-Pacific region such as Taiwan, South Korea, Japan, and China are investing more in semiconductor manufacturing to meet the increasing demand for consumer electronic products. This detailed market research study provides detailed qualitative and quantitative analysis of the global chemical mechanical planarization market. It provides a comprehensive review of major market drivers, restraints, opportunities, challenges, and key issues in the market.

By Jeff Dorsch

Chemical mechanical planarization (CMP) technology has been around for a long time. In addition to the semiconductor industry, CMP has applications in data storage, polishing the rigid disks and magnetic heads of hard-disk drives.

Those interested in learning about developments in CMP for hard drives and integrated circuits would do well to attend the CMP Technical and Market Trends session on Thursday, July 16, at 11 a.m. in the TechXPOT North area of Moscone Center’s North Hall. Representatives of Intel, HGST, Entegris, TDK, and other companies will be speaking.

While 450-millimeter wafers haven’t been much in the news this year, Thursday’s session will include a presentation by the Global 450 Consortium, with speakers from the College of Nanoscale Science + Engineering (CNSE) and SEMATECH.

CNSE is part of the SUNY Polytechnic Institute in Albany, N.Y., which also contains the Chemical Mechanical Planarization Center, a joint program with SEMATECH. Mitsubishi Chemical joined the program this spring.

While CMP is still used for its traditional polishing applications for interlayer dielectrics, it’s also finding employment in more advanced applications, such as bulk oxide polishing, shallow trench isolation, “stop on poly” isolation, and polishing of various dielectrics in advanced transistor designs.

CMP includes consumable products, polishing pads and slurries. Dow Chemical is the leading vendor in polishing pads, while Cabot Microelectronics dominates the CMP slurry market.

Late last month, Applied Materials and Cadence Design Systems announced that they are collaborating on optimizing the CMP process through silicon characterization and modeling for ICs with 14-nanometer features, and beyond that process node. Cadence, one of the leading vendors of electronic design automation software and services, will provide its CMP Predictor and CMP Process Optimizer tools. Applied will employ its Reflexion LK Prime CMP system.

“From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster,” Derek Witty, vice president and general manager of Applied’s CMP Products Group, said in a statement.

Whatever your level of expertise in CMP, SEMICON West 2015 will help you polish up your knowledge of the field.

Entegris, Inc. today announced a new product for its VaporSorb line of airborne molecular contamination (AMC) filters. The new filter was created as an “all-in-one,” single-filter solution for capturing critical AMC in the chemical mechanical planarization process, or CMP, in semiconductor manufacturing. VaporSorb, which is a leading brand of filter used in cleanroom environments and for process tools during key steps in manufacturing, is the first such filter available for CMP process tools that protects against weak acids as well as other contaminants.

The new filter was designed specifically for CMP tools to provide balanced lifetimes for all critical AMC in a single filter which avoids the complexities of multi-filter handling. In addition, the filter retains the VaporSorb brand’s industry-leading service life to reduce both tool downtime and cost of ownership.

“Yield concerns in the CMP process, just as in the photolithography process, can be addressed by providing complete AMC protection. This means protecting against weak acids, as well as strong acids and other contaminants,” stated Entegris Product Marketing Manager for AMC Filtration Solutions, Marc Venet. “With VaporSorb CMP, we have a single solution that completely addresses AMC-induced corrosion defects in CMP processes.”

Examples of weak acids include acetic and formic acids (acetate; CH3COO and formate; HCOO) and nitrous acid (nitrite; NO2). Strong acids include HNO3, SO2, H2SO4 and HCl. These contaminants are causing concerns regarding defects and yield in CMP processes.

In July, the company launched the industry’s first “four-in-one” filter, the VaporSorb TRK for photolithography tools, to capture airborne organics, bases, strong acids and weak acids. VaporSorb filters use Entegris’ own unique mix of materials to capture airborne molecular contaminants, which are tailored to create application- and fab-specific filter solutions.

Dow Electronic Materials, a business unit of The Dow Chemical Company, today introduced the IKONIC 4000 series of chemical mechanical planarization (CMP) polishing pads. This series of pads are initially targeting ceria-based applications.

“The pads are highly tunable and can be customized to address process specific requirements,” said Colin Cameron, director of marketing CMPT Dow Electronic Materials. “Dow’s volume manufacturing methods and commitment to process control further enhance performance by ensuring consistency and reliability in our customer’s processes.”

The new IKONIC 4000 series balances the historic trade-off associated with cutting edge planarization requirements and low defectivity. The novel chemistries deliver removal rate stability over pad life, making them ideal for the challenges associated with ceria based polishing applications. The IKONIC 4000 series delivers step-out defectivity performance representing a 70 percent improvement when compared with the industry-standard IC1000 polishing pad.

Developed in collaboration with Dow’s customers, the IKONIC 4000 series is available in multiple formulations featuring a range of hardness and porosity. This allows for customization to address specific customer requirements. The pads are also optimized for easier conditioning and to maintain consistent texture throughout the pad’s lifetime.