Category Archives: Polishing Pads

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Entegris, Inc., a developer of yield-enhancing materials and solutions, today announced new post-chemical mechanical planarization (post-CMP) cleaning solutions for semiconductor manufacturing. The new PlanarClean AG family of products were designed for use in 10nm processes and below, and add to Entegris’ portfolio of post-CMP cleaning solutions.

“Entegris has been the industry leader in post-CMP cleaning for many years. Our PlanarClean family products have been widely used in wafer fabs around the world. To address greater complexity of wafer production at the leading-edge nodes due to the addition of many new materials, such as cobalt and tungsten, we carefully re-formulated our PlanarClean solution to provide superior cleaning without damaging advanced films or new materials,” said Cuong Tran, director of post-CMP cleans for Entegris. “PlanarClean AG meets the needs for advanced processes, while also conforming to new safety guidelines outlined by our customers.”

The CMP process in silicon wafer production consists of a mechanical polishing step which utilizes a chemical slurry formulation to remove unwanted conductive or dielectric materials from the surface of the integrated device, achieving a flat and smooth surface upon which additional layers of integrated circuitry are built. The post-CMP cleaning step removes nanoparticles to minimize potential wafer defects while maintaining the integrity of the layers of materials already in place.

Changes to the number and types of films and materials exposed during cleaning in advanced processes have highlighted a need for specifically formulated cleans. In addition, changes to the particles used in slurries have rendered many of the traditional post-CMP cleaners ineffective and inefficient for leading-edge technologies, specifically in Front-End-of-Line (FEOL) processes. These challenges are now pushing semiconductor manufacturers to consider formulated cleans over commodity cleans.

PlanarClean AG formulated solutions meet these needs by providing one-step, superior cleaning in advanced processes that include copper, cobalt and tungsten, while protecting the underlying thin films and materials. Its proprietary formulation offers increased performance through enhanced reliability and yield, low to zero corrosion and defects and increased queue time. In addition, PlanarClean AG provides a cost-of-ownership advantage by reducing the amount of chemistry required in the cleaning step, and meets the latest EHS safety requirements for fab chemistries. The products have been successfully evaluated in multiple leading-edge fabs and are currently available to all customers.

 

Chemical mechanical planarization (CMP) is a critical process technology step in the semiconductor wafer fabrication process. In this process step, the top surface of the wafer is polished or planarized to create a flat surface.

The CMP tool is comprised a rotating platen, slurry, pad, holding ring, brush, and pad conditioner. The mechanical element of this system applies downward pressure to a wafer surface, while the chemical reaction increases the material removal rate. The value chain of the CMP market consists of different players, including semiconductor material suppliers, CMP integrated solution providers, semiconductor wafer suppliers, semiconductor device manufacturers, slurry & pad manufacturers, technology solution providers, and CMP equipment manufacturers.

While CMP is still used for its traditional polishing applications for interlayer dielectrics, it’s also finding employment in more advanced applications, such as bulk oxide polishing, shallow trench isolation, “stop on poly” isolation, and polishing of various dielectrics in advanced transistor designs.

According to a recent market research report published by MarketsandMarkets, the global CMP market is expected to reach $4.94 Billion by 2020, at an estimated CAGR of 6.83% from 2015 to 2020.

Though the CMP market is at the mature stage, it still continues to evolve depending on the end users. The industry is being forced to adopt much innovation in process technologies and applications; as a result, different CMP processes have been evolved with technology nodes and newer applications such as MEMS, advanced packaging, and advanced substrates.

Applied Materials, Inc. (U.S.) and Ebara Corporation (Japan) are the major CMP equipment suppliers. Phoenix-based Entrepix offers unique CMP foundry services.

CMP includes consumable products, polishing pads and slurries. This CMP consumables market is dominated by major market players such as Cabot Microelectronics Corporation (U.S.), Fujimi Incorporated (Japan), and Dow Electronic Materials (U.S.).

Success in CMP lies in optimizing the many process variables. In addition to wafer variables such as film type and pattern density, CMP variables include: time, pressure (force applied to the wafer and pad), velocity, temperature, slurry feed rate, polishing motion, slurry chemistry and pH potential, slurry particle size, pad elasticity, pad hardness and pad condition method. An optimized CMP process also depends on removal rates of the film being planarized, adhesion stability of the film, minimal defects such as scratchs or pits, minimal corrosion (in the case of Cu), and the adhesion of organic or inorganic surface residues formed during the CMP process.

With alternate channel materials on the horizon for future logic transistor, III-V materials such as gallium-arsenide (GaAs), gallium-indium-phosphide (GaInP), and indium-phosphide (InP) are now in R&D which leads to questions regarding direct process costs as well as indirect EHS costs. Much of the concern involves the possible reaction and release of toxic hydrides such as arsine, and phosphine. SEMATECH worked with imec to monitor hydrides produced during CMP processes for high-mobility compound semiconductors.

Suggested Additional Reading:

Chemical Mechanical Planarization: Historical Review and Future Direction

Northern California Chapter of American Vacuum Society: CMP Users Group

CMP Technology Evolving to Engineer Surfaces

Reduced defectivity and cost of ownership of copper CMP cleans

Safe CMP slurries for future IC materials

The rule of three

By Jeff Dorsch

Chemical mechanical planarization (CMP) technology has been around for a long time. In addition to the semiconductor industry, CMP has applications in data storage, polishing the rigid disks and magnetic heads of hard-disk drives.

Those interested in learning about developments in CMP for hard drives and integrated circuits would do well to attend the CMP Technical and Market Trends session on Thursday, July 16, at 11 a.m. in the TechXPOT North area of Moscone Center’s North Hall. Representatives of Intel, HGST, Entegris, TDK, and other companies will be speaking.

While 450-millimeter wafers haven’t been much in the news this year, Thursday’s session will include a presentation by the Global 450 Consortium, with speakers from the College of Nanoscale Science + Engineering (CNSE) and SEMATECH.

CNSE is part of the SUNY Polytechnic Institute in Albany, N.Y., which also contains the Chemical Mechanical Planarization Center, a joint program with SEMATECH. Mitsubishi Chemical joined the program this spring.

While CMP is still used for its traditional polishing applications for interlayer dielectrics, it’s also finding employment in more advanced applications, such as bulk oxide polishing, shallow trench isolation, “stop on poly” isolation, and polishing of various dielectrics in advanced transistor designs.

CMP includes consumable products, polishing pads and slurries. Dow Chemical is the leading vendor in polishing pads, while Cabot Microelectronics dominates the CMP slurry market.

Late last month, Applied Materials and Cadence Design Systems announced that they are collaborating on optimizing the CMP process through silicon characterization and modeling for ICs with 14-nanometer features, and beyond that process node. Cadence, one of the leading vendors of electronic design automation software and services, will provide its CMP Predictor and CMP Process Optimizer tools. Applied will employ its Reflexion LK Prime CMP system.

“From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster,” Derek Witty, vice president and general manager of Applied’s CMP Products Group, said in a statement.

Whatever your level of expertise in CMP, SEMICON West 2015 will help you polish up your knowledge of the field.

Dow Electronic Materials, a business unit of The Dow Chemical Company, today introduced the IKONIC 4000 series of chemical mechanical planarization (CMP) polishing pads. This series of pads are initially targeting ceria-based applications.

“The pads are highly tunable and can be customized to address process specific requirements,” said Colin Cameron, director of marketing CMPT Dow Electronic Materials. “Dow’s volume manufacturing methods and commitment to process control further enhance performance by ensuring consistency and reliability in our customer’s processes.”

The new IKONIC 4000 series balances the historic trade-off associated with cutting edge planarization requirements and low defectivity. The novel chemistries deliver removal rate stability over pad life, making them ideal for the challenges associated with ceria based polishing applications. The IKONIC 4000 series delivers step-out defectivity performance representing a 70 percent improvement when compared with the industry-standard IC1000 polishing pad.

Developed in collaboration with Dow’s customers, the IKONIC 4000 series is available in multiple formulations featuring a range of hardness and porosity. This allows for customization to address specific customer requirements. The pads are also optimized for easier conditioning and to maintain consistent texture throughout the pad’s lifetime.