Category Archives: ALD Equipment


As the world of advanced manufacturing enters the sub-nanometer scale era, it is clear that ALD, MLD and SAM represent viable options for delivering the required few-atoms-thick layers required with uniformity, conformality, and purity.

BY BARRY ARKLES, JONATHAN GOFF, Gelest Inc., Morrisville PA; ALAIN E. KALOYEROS, SUNY Polytechnic Institute, Albany, NY

Device and system technologies across several industries are on the verge of entering the sub-nanometer scale regime. This regime requires processing techniques that enable exceptional atomic level control of the thickness, uniformity, and morphology of the exceedingly thin (as thin as a few atomic layers) film structures required to form such devices and systems.[1]

In this context, atomic layer deposition (ALD) has emerged as one of the most viable contenders to deliver these requirements. This is evidenced by the flurry of research and devel- opment activities that explore the applicability of ALD to a variety of material systems,[2,3] as well as the limited introduction of ALD TaN in full-scale manufacturing of nanoscale integrated circuitry (IC) structures.[4] Both the success and inherent limitations of ALD associated with repeated dual-atom interactions have stimulated great interest in additional self-limiting deposition processes, particularly Molecular Layer Deposition (MLD) and Self- Assembled Monolayers (SAM). MLD and SAM are being explored both as replacements and extensions of ALD as well as surface modification techniques prior to ALD.[5]

ALD is a thin film growth technique in which a substrate is exposed to alternate pulses of source precursors, with intermediate purge steps typically consisting of an inert gas to evacuate any remaining precursor after reaction with the substrate surface. ALD differs from chemical vapor deposition (CVD) in that the evacuation steps ensure that the different precursors are never present in the reaction zone at the same time. Instead, the precursor doses are applied as successive, non-overlapping gaseous injections. Each does is followed by an inert gas purge that serves to remove both byproducts and unreacted precursor from the reaction zone.

The fundamental premise of ALD is based on self-limiting surface reactions, wherein each individual precursor-substrate interaction is instantaneously terminated once all surface reactive sites have been depleted through exposure to the precursor. For the growth of binary materials, each ALD cycle consists of two precursor and two purge pulses, with the thickness of the resulting binary layer per cycle (typically about a monolayer) being determined by the precursor-surface reaction mode. The low growth rates associated with each ALD cycle enable precise control of ultimate film thickness via the application of repeated ALD cycles. Concurrently, the self-limiting ALD reaction mechanisms allow excellent conformality in ultra-high-aspect-ratio nanoscale structures and geometries.[6]

A depiction of an individual ALD cycle is shown in FIGURE 1. In Fig. 1(a), a first precursor A is introduced in the reaction zone above the substrate surface.

Screen Shot 2018-03-01 at 3.03.03 PM

Precursor A then adsorbs intact or reacts (partially) with the substrate surface to form a first monolayer, as shown in Fig. 1(b), with any excess precursor and potential byproducts being evacuated from the reaction zone through a subsequent purge step. In Fig. 1(d), a second precursor Y is injected into the reaction zone and is made to react with the first monolayer to form a binary atomic layer on the substrate surface, as displayed in Fig. 1(e). Again, all excess precursors and reaction byproducts are flushed out with a second purge step 1(f). The entire process is performed repeatedly to achieve the targeted binary film thickness.

In some applications, a direct or remote plasma is used as an intermediate treatment step between the two precursor-surface interactions. This treatment has been reported to increase the probability of surface adsorption by boosting the number of active surface sites and lowering the reaction activation energy. As a result, such treatment has led to increased growth rates and reduce processing temperatures.[7]

A number of benefits have been cited for the use of ALD, including high purity films, absence of particle contami- nation and pin-holes, precise control of thickness at the atomic level, excellent thickness uniformity and step coverage in complex via and trench topographies, and the ability to grow an extensive array of binary material systems. However, issues with surface roughness and large surface grain morphology have also been reported. Another limitation of ALD is the fact that it is primarily restricted to single or binary material systems. Finally, extremely slow growth rates continue to be a challenge, which could potentially restrict ALD’s applicability to exceptionally ultrathin films and coatings.

These concerns have spurred a renewed interest in other molecular level processing technologies that share the self-limiting surface reaction characteristics of ALD. Chief among them are MLD and SAM. MLD refers principally to ALD-like processes that also involve successive precursor-surface reactions in which the various precursors never cross paths in the reaction zone. [8] However, while ALD is employed to grow inorganic material systems, MLD is mainly used to deposit organic molecular films. It should be noted that this definition of MLD, although the most common, is not yet universally accepted. An alternative characterization refers to MLD as a process for the growth of organic molecular components that may contain inorganic fragments, yet it does not exhibit the self-limiting growth features of ALD or its uniformity of film thickness and step coverage.[2]

A depiction illustrating a typical MLD cycle, according to the most common definition, is shown in FIGURE 2. In Fig. 2(a), a precursor is introduced in the reaction zone above the substrate surface. Precursor C adsorbs to the substrate surface and is confined by physisorption (Fig. 2(b)). The precursor then undergoes a quick chemisorption reaction with a significant number of active surface sites, leading to the self-limiting formation of molecular attachments in specific assemblies or regularly recurring structures, as displayed in Fig. 2(c). These structures form at significantly lower process temperatures compared to traditional deposition techniques.

Screen Shot 2018-03-01 at 3.03.09 PM

To date, MLD has been successfully applied to grow exceptionally thin films for applications as organic, inorganic, and hybrid organic-inorganic dielectrics and polymers for IC applications; [1,9] nanoprobes for in-vitro imaging and interrogation of biological cells; [10] photoluminescent devices; [7] and lithium-ion battery electrodes.[11]

SAM is a deposition technique that involves the spontaneous adherence of organized organic structures on a substrate surface. Such adherence takes place through adsorption from the vapor or liquid phase through relatively weak interactions with the substrate surface. Initially, the structures are adsorbed on the surface by physisorption through, for instance, van der Waals forces or polar interactions. Subsequently, the self-assembled monolayers become slowly confined by a chemisorption process, as depicted in FIGURE 3.

Screen Shot 2018-03-01 at 3.03.18 PM

The ability of SAM to grow layers as thin as a single molecule through chemisorption-driven interactions with the substrate has triggered enthusiasm for its potential use in the formation of “near-zero-thickness” activation or barrier layers. It has also sparked interest in its appli- cability to area-selective or area-specific deposition. Molecules can be directed to exhibit preferential reactions with specific segments of the underlying substrate rather than others to facilitate or obstruct subsequent material growth. This feature makes SAM desirable for incorpo- ration in area-selective ALD (AS-ALD) or CVD (AS-CVD), where the SAM-formed layer would serve as a foundation or blueprint to drive AS-ALD or AS-CVD. [12,13]

To date, SAM has been effectively employed to form organic layers as thin as a single molecule for applications as organic, inorganic, and hybrid organic-inorganic dielec- trics; polymers for IC applications; [13,14] encapsulation and barrier layers for IC metallization; [15] photoluminescent devices; [5] molecular and organic electronics; [16] and liquid crystal displays.[17]

As the world of advanced manufacturing enters the sub-nanometer scale era, it is clear that ALD, MLD and SAM represent viable options for delivering the required few-atoms-thick layers required with uniformity, conformality, and purity. By delivering the constituents of the material systems individually and sequentially into the processing environment, and precisely controlling the resulting chemical reactions with the substrate surface, these techniques enable excellent command of processing parameters and superb management of the target specifications of the resulting films. In order to determine whether one or more ultimately make it into full-scale manufacturing, a great deal of additional R&D is required in the areas of understanding and establishing libraries of fundamental interactions, mechanisms of source chemistries with various substrate surfaces, engineering viable solutions for surface smoothness and rough morphology, and developing protocols to enhance growth rates and overall throughput.


1. Belyansky, M.; Conti, R.; Khan, S.; Zhou, X.; Klymko, N.; Yao, Y.; Madan, A.; Tai, L.; Flaitz, P.; Ando, T. Silicon Compat. Mater. Process. Technol. Adv. Integr. Circuits Emerg. Appl. 4 2014, 61 (3), 39–45.
2. George, S. M.; Yoon, B. Mater. Matters 2008, 3 (2), 34–37. 3. George, S. M.; Yoon, B.; Dameron, A. A. Acc. Chem. Res.
2009, 42 (4), 498–508.
4. Graef, E.; Huizing, B. International Technology Roadmap for
Semiconductors 2.0, 2015th ed.; 2015.
5. Kim, D.; Zuidema, J. M.; Kang, J.; Pan, Y.; Wu, L.; Warther, D.; Arkles, B.; Sailor, M. J. J. Am. Chem. Soc. 2016, 138 (46),
6. George, S. M. Chem. Rev. 2010, 110 (1), 111–131.
7. Provine, J.; Schindler, P.; Kim, Y.; Walch, S. P.; Kim, H. J.; Kim,
K. H.; Prinz, F. B. AIP Adv. 2016, 6 (6).
8. Räupke, A.; Albrecht, F.; Maibach, J.; Behrendt, A.; Polywka,
A.; Heiderhoff, R.; Helzel, J.; Rabe, T.; Johannes, H.-H.; Kowalsky, W.; Mankel, E.; Mayer, T.; Görrn, P.; Riedl, T. 226th Meet. Electrochem. Soc. (2014 ECS SMEQ) 2014, 64 (9), 97–105.
9. Fichtner, J.; Wu, Y.; Hitzenberger, J.; Drewello, T.; Bachmann, J. ECS J. Solid State Sci. Technol. 2017, 6 (9), N171–N175.
10. Culic-Viskota, J.; Dempsey, W. P.; Fraser, S. E.; Pantazis, P. Nat. Protoc. 2012, 7 (9), 1618–1633.
11. Loebl, A. J.; Oldham, C. J.; Devine, C. K.; Gong, B.; Atanasov, S. E.; Parsons, G. N.; Fedkiw, P. S. J. Electrochem. Soc. 2013, 160 (11), A1971–A1978.
12. Sundaram, G. M.; Lecordier, L.; Bhatia, R. ECS Trans. 2013, 58 (10), 27–37.
13. Kaufman-Osborn, T.; Wong, K. T. Self-assembled monolayer blocking with intermittent air-water exposure. US20170256402 A1, 2017.
14. Arkles, B.; Pan, Y.; Kaloyeros, A. ECS Trans. 2014, 64 (9), 243–249.
15. Tan, C. S.; Lim, D. F. In ECS Transactions; 2012; Vol. 50, pp 115–123.
16. Kong, G. D.; Yoon, H. J. J. Electrochem. Soc. 2016, 163 (9), G115–G121.
17. Wu, K. Y.; Chen, W. Y.; Wang, C.-H.; Hwang, J.; Lee, C.-Y.; Liu, Y.-L.; Huang, H. Y.; Wei, H. K.; Kou, C. S. J. Electrochem. Soc. 2008, 155 (9), J244.

Stanford University researchers sponsored by Semiconductor Research Corporation (SRC) have developed a new area selective atomic layer deposition (ALD) process that promises to accelerate the manufacturing of higher performing, more energy efficient semiconductors.

It is well known that next-generation electronic, optoelectronic and sensing devices that contain nanoscale dimensions face increasingly difficult materials and fabrication challenges as the downward scaling of these devices continues. Conventional semiconductor manufacturing processes are time-consuming and expensive, in part due to the need for lithographic patterning. The Stanford research leverages simple ALD and etching processes that eliminate this lithography step and improve selective deposition of dielectric materials by more than 10 times in film thickness compared to similar advanced processes.

Due to difficulties of current top-down fabrication processes that contain multiple deposition, lithography and etching steps, along with problems with misalignment in lithography, using an alternative approach in which the desired materials are directly and selectively deposited would significantly facilitate the process, according to the Stanford team.

“Our technology is a promising candidate for overcoming the challenges of top-down processing and misalignment because it greatly improves the ability to perform selective deposition of materials. This research introduces a novel processing method to meet the increasingly difficult materials challenges associated with new devices,” said Dr. Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.

Current approaches utilize lithography for nanoscale patterning. Using lithography and etching for fabrication of 2D or 3D structures often results in misaligned features and causes a risk of shorting or high resistant areas. However, selective deposition using ALD can reduce these risks and reduce the process time and steps.

Bent explained that selective deposition allows layers of material to be added onto a substrate only where desired without the need for additional lithography steps. However, the high level of selectivity needed for a manufacture-worthy process has not yet been achieved in area selective deposition studies. In addition, most methods for area selective deposition require long processing times.

The Stanford research has been focused on selective deposition of dielectric materials on metal/dielectric patterns. These type of structures can be found in interconnects and back-end-of-line (BEOL) processing. With ALD being used in other stages of the device fabrication process as well, the results from the Stanford experiments can potentially be applied to a variety of nanoscale electronic, optoelectronic and sensing devices.

The research developments occurred during the second year of research on the topic, and the Stanford team is continuing to explore new methods for area selective ALD to improve both selectivity and manufacturability.

“The Stanford team’s research has shown for the first time that, by following selective deposition of a dielectric material using pre-treatment by an inhibitory material, they can significantly reduce the process time (from 48 hours to less than 1 hour) and also improve the limits of selective deposition of dielectrics by more than 10 times,” said Kwok Ng, Senior Science Director of Nanomanufacturing Materials and Processes at SRC.

CVD Source Materials

December 17, 2015

Reaction materials for chemical vapor deposition (CVD) and atomic layer deposition (ALD) are typically delivered into the chamber in a gaseous form. CVD polycrystalline silicon, for example, is deposited from trichlorosilane (SiHCl3) or silane (SiH4), using the following reactions:

SiH3Cl → Si + H2 + HCl
SiH4 → Si + 2 H2

This reaction is usually performed in LPCVD systems, with either pure silane feedstock, or a solution of silane with 70–80% nitrogen. Polysilicon may be grown directly with doping, if gases such as phosphine, arsine or diborane are added to the CVD chamber.

Silicon dioxide (usually called simply “oxide” in the semiconductor industry) may be deposited by several different processes. Common source gases include silane and oxygen, dichlorosilane (SiCl2H2) and nitrous oxide (N2O), or tetraethylorthosilicate (TEOS; Si(OC2H5)4). The reactions are as follows:

SiH4 + O2 → SiO2 + 2 H2
SiCl2H2 + 2 N2O → SiO2 + 2 N2 + 2 HCl
Si(OC2H5)4 → SiO2 + byproducts

CVD source materials are typically gases, such as silane and nitrogen, but can also be liquids: There are now a larger variety of liquid sources used in the semiconductor, FPD and PV manufacturing processes.

CVD Sources

The graph above shows the different possible states of matter. There are two ways to get from a liquid to a gaseous state. The first method involves increasing the temperature while holding the pressure steady, as indicated by the arrow with the broken line. This method is commonly used in everyday settings—to boil water and convert it to steam, for example. Heating a liquid takes time, however, which makes rapid vaporization difficult. On the other hand, one can also heat the liquid in advance and then abruptly reduce the pressure, as illustrated by the arrow with the solid line. The pressure in the vaporization section of the injector can be reduced instantaneously, and this makes it possible to vaporize a liquid source instantaneously.

Chemical Vapor Deposition

December 11, 2015

Chemical vapor deposition (CVD) is used to produce high-purity thin films. In a typical CVD process, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Frequently, volatile byproducts are also produced, which are removed by gas flow through the reaction chamber.

Microfabrication processes widely use CVD to deposit materials in various forms, including: monocrystalline, polycrystalline, amorphous, and epitaxial. These materials include: silicon, carbon fiber, filaments, carbon nanotubes, SiO2, silicon-germanium, tungsten, silicon carbide, silicon nitride, silicon oxynitride, titanium nitride, and various high-k dielectrics. The CVD process is also used to produce synthetic diamonds.

Applications include shallow-trench isolation, pre-metal dielectric, inter-metal dielectric, and passivation. CVD processes are also important in strain engineering that uses compressive or tensile stress films to enhance transistor performance through improved conductivity.

Additional Reading

Taking 2D materials from lab to fab, and to technology

New materials require new approaches

Deposition equipment market witnesses a year of significant change

April 28, 2011 — ASM International N.V. (NASDAQ: ASMI and Euronext Amsterdam: ASM) received multiple system orders for its plasma enhanced atomic layer deposition (PEALD) reactor from a leading memory customer in Asia. Second, the company qualified a new PEALD oxide application with a memory manufacturer for the 2X nm node.

“Our innovative PEALD technology is seeing strong market validation with high-volume business from multiple top tier memory customers,” said Tominori Yoshida, general manager of ASM’s Plasma Products business unit. “Our increasing range of production-ready PEALD applications position us to support memory manufacturers now and as they move towards the challenging 1X nm node.”

The PEALD systems were ordered by a leading memory customer for high-volume manufacturing and will be installed in multiple facilities in Asia. The reactors will be used to deposit dielectrics for advanced lithography double patterning applications at the 3X nm technology node and below. This order represents the second major manufacturer to adopt ASM’s PEALD system for use in double patterning in high volume manufacturing.

ASM also qualified a new oxide application for an advanced PEALD SiO layer that targets manufacturing at the 2X nm node and below. The new application is expected to enter volume production later this year with a different Asia-based manufacturer.

ASM’s PEALD reactors are optimized to deposit dielectrics including SiO, SiN and SiCN. The process delivers conformal thin films at low temperatures, for double patterning lithography technologies where thin dielectrics are deposited over temperature-sensitive photoresists for critical dimension control and pitch reduction.

Each of the systems ordered includes multiple PEALD reactors implemented on ASM’s XP platform. The XP is a production-proven standard platform that can be configured with plasma enhanced chemical vapor deposition (PECVD), thermal ALD or PEALD reactors.

Also see: Below 22nm, spacers get unconventional: Interview with ASM

ASM International N.V. and its subsidiaries design and manufacture equipment and materials used to produce semiconductor devices, wafer processing (Front-end segment) as well as assembly and packaging (Back-end segment). ASM International’s common stock trades on NASDAQ (symbol ASMI) and the Euronext Amsterdam Stock Exchange (symbol ASM). For more information, visit ASMI’s website at

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Executive Overview

Atomic layer deposition (ALD) will be used in multiple areas of the 22nm logic process flow despite initial concerns about the technology’s viability for high-volume manufacturing. Each application space creates a unique need for manufacturing equipment configuration and technology variations – from single-wafer ALD systems for extremely tight process control, batch ALD systems for low COO operation, to mini-batch systems for a meld of COO and process control for multi-layer applications. Selection of the appropriate manufacturing toolset is as critical to eventual technology adoption as the process itself, and final implementation will require the correct toolsets to ensure that the ALD films can be deposited in a cost efficient manner.

M. Verghese, ASM, Phoenix, AZ USA;  J. W. Maes, ASM, Leuven, Belgium; N. Kobayashi, ASM, Tokyo, Japan

Since its invention in the 1970s, atomic layer deposition (ALD) has been used in a variety of applications ranging from electroluminescence display manufacturing to industrial coatings [1]. Over the last decade, the semiconductor industry has slowly been adopting ALD reactors for critical layers where the benefits of ALD enable scaling and improved performance. With the upcoming transition to 22nm, process flows are being adapted to allow ever more ALD layers. As a variant of chemical vapor deposition (CVD), ALD techniques capitalize on surface saturation reactions to deposit extremely smooth, dense, and highly conformal films through a process that is relatively insensitive to fluctuations in process temperature and reactant flux. The ALD process relies on sequential introduction of the reactants into the reaction space, separated by inert gas purges, such that repetition of the ALD cycles results in a monolayer by monolayer growth of the deposited film. Thickness of the film can then be precisely controlled by adjusting the number of ALD cycles.

Process considerations for single-wafer tools

DRAM manufacturers were the first to use ALD to ensure conformal deposition of high-k dielectrics in high aspect ratio capacitor structures. Aggressive scaling of device dimensions and the subsequent requirement of low thermal budgets to control dopant diffusion continue to push the entire semiconductor industry to displace conventional CVD, plasma enhanced CVD (PECVD), and sputtering techniques with novel ALD processes in critical areas such as transistor gate stack formation and spacer defined double patterning. The low throughputs that are typically associated with ALD techniques have been a barrier to its adoption in mainstream production flows. However, these concerns are being addressed by intelligent equipment design to optimize the ALD process and hardware for individual application spaces. At the 22nm node, the logic industry will use ALD in several key process steps – both in front end transistor formation and in back end metallization and interconnect. Each application has highly specific requirements and calls for different hardware configurations for the optimal production solution.

Single-wafer ALD chambers are ideal when the application demands extremely thin films with precise thickness and uniformity control. Single-wafer systems can also most easily handle difficult precursor chemistries such as low vapor pressure, decomposition prone liquids and solids since ALD cycle times are typically short (in the order of a few seconds) and the source delivery systems can be placed in close proximity to the reaction chamber. Purge efficiency can be optimized relatively easily in single-wafer systems and as a result, these chambers are ideal for pure ALD deposition.

Figure 1. Need for complete ALD high-k/metal gate solution in 22nm logic transistors.

Single-wafer ALD systems also have high precursor utilization efficiencies and hence, are a good fit for processes that use expensive precursor materials. For example, high-k dielectrics and metal gates for transistor gate oxide and electrodes require deposition of films as thin as 10Å while maintaining within wafer uniformities of <1%, 1σ. Hafnium-based high-k gate oxides typically use hafnium chloride, a solid precursor, for its excellent electrical performance when compared to metal organic chemistries [2]. Single-wafer systems tend to be the best choice for gate oxide deposition as they are very capable of delivering this highly condensable precursor. Furthermore, replacement gate devices require multiple, conformal metal films <50Å thick to ensure that space remains for a gate contact fill (Fig. 1). Single-wafer plasma-enhanced ALD (PEALD) is also used for the deposition of silicon oxide, silicon nitride, and silicon carbon nitride gate spacers. PEALD enables low-temperature deposition (<400°C), excellent conformality, and lower wet etch rates than films deposited by plasma enhanced CVD (PECVD). Film stress can also be varied from compressive to tensile by varying plasma processing conditions [3]. Techniques such as PVD and CVD are unable to attain the step coverage, thickness control, and cross-wafer uniformities required for such an application; single-wafer ALD has been gradually replacing these techniques in high performance logic gate structures since the 45nm node [4]. By the 22nm node, all primary gate stack materials will be deposited by ALD processes. The advent of three-dimensional architectures such as FinFETs, and the film conformality requirements that come therewith, will ensure that ALD will be the deposition technique of choice for the next several generations of advanced logic gate stack structures.

Batch tools for thicker films/high-aspect ratios

When film thicknesses are less than one hundred angstroms thick, ALD process times are typically no longer than a few minutes. Single-wafer tools then give acceptable throughput performance and short turn-around times. However, for some applications, the process times are inevitably longer. This can occur when thicker layers are required or when films have to be deposited in high-aspect ratio structures. Substrates with high-aspect ratio structures have a larger surface area than planar wafers and usually require a higher precursor dose and subsequently need longer pulses and purge times to enable effective gas transport into and out of the structures. Also, some ALD chemistries can have lower growth rates than others and some processes may require relatively long pulses to ensure complete surface reactions to achieve the desired film quality.

The throughput and cost-of-ownership (COO) performance of batch ALD approaches with ~100 wafer loads in one reactor can be substantially better than that of single-wafer systems. Pulse and purge times have to be longer in batch reactors because the volume of the reactor is larger and the gas transport depends more on diffusion (rather than forced convection) than in single-wafer systems. However, the total increase in cycle time is smaller than a factor of 100, more on the order of 10-50. Process optimization in a batch system is more complex than in a single-wafer system but for ALD chemistries that result in self-limiting ALD surface reactions, relatively good uniformities and step coverage can still be achieved. The precursor flow and total dose that is delivered to the batch reactor is typically much larger than in single-wafer applications, especially when high aspect ratio device structures are involved. However, techniques such as direct liquid injection (DLI) can be used to mitigate precursor dose delivery issues as long as the vapor pressure of the precursor is sufficiently high. Low vapor pressure precursors (which also can be solid powders) are more troublesome in batch equipment due to risk of condensation and decomposition associated with the high residence time in the reactors.

ALD titanium nitride using titanium chloride and ammonia meet all the criteria required to make batch processing an attractive option. Titanium nitride films are used in several applications in logic devices: electrodes for replacement gates, electrodes for embedded DRAM devices, barrier films in tungsten contacts, and through- silicon-via (TSV) structures. Required film thicknesses are in the range of 20−150Å.

Figure 2. Step coverage of batch pulsed CVD TiN film in 32:1 trenches.

The process can be run in two modes: a strict ALD mode where completely separated titanium chloride and ammonia pulses are used (resulting in a growth rate of ~0.3Å/cycle), but also in a second mode in which one of the two pulses is actually a CVD pulse. In the pulsed CVD mode, a higher (3-5x) growth rate can be achieved. Batch reactors are able to run ALD-like processes such as pulsed CVD, with good results. The resulting film resistivity is a function of deposition temperature. In the ALD mode, one can use about 100°C lower deposition temperature to achieve the same resistivity as films deposited by the pulsed CVD mode [5]. Figure 2 shows an example of the deposition of a thicker layer of titanium nitride in a high aspect ratio structure. A highly conformal film is achieved, with step coverage of better than 95%, using the ALD-like pulsed CVD process mode in a batch reactor. Batch reactors can run at a throughput of greater than 30wph per reactor for 10nm films. These results demonstrate that batch-type ALD reactors are an attractive tool choice for some of the new ALD applications in future logic devices.

Mini-batch or multi-wafer ALD systems

When deposition of thicker films using complex precursors is required at reasonable throughputs and with short turn around times, a mini-batch or multi-single-wafer ALD system is the most appropriate. Mini-batch and multi-single-wafer ALD reactors meld the flexibility of single-wafer systems with the productivity of batch reactors. Typically, a mini-batch reactor processes four to five wafers together in one reactor and a multi-single-wafer system processes four to five wafers in individual reactors packaged in one module. These types of reactors can result in improved COO when compared to single-wafer systems as they occupy less floor space and rely on fewer, shared sub-systems. For example, gas panels, RF systems, and pumps can be combined for use on a mini-batch system whereas single-wafer tools would require multiple individual sub-systems. In addition, creative design of mini-batch systems can allow the use of direct plasma to enable plasma-enhanced ALD processes.

Spacer-defined double-patterning (SDDP) will likely be introduced to manufacture highly scaled lines and spacers for 22nm logic devices. In this technology, a conformal, ALD silicon oxide (SiO2) film is deposited directly on photoresist at extremely low temperatures. This is followed by an anisotropic etch-back process that results in the formation of SiO2 spacers that act as hard masks with smaller pitches. For this application, a mini-batch (multi-single-wafer) system is useful – ensuring high throughput in a system that can utilize direct plasma to enable deposition at near room temperatures. PEALD SiO2 using a mini-batch system results in conformal deposition at low-temperatures (<100°C) with within-wafer and wafer-to-wafer uniformity < 1%, three sigma. Throughputs can be achieved at >45wph per reactor at 20nm film thickness with high equipment utilization due to in situ remote plasma cleaning capability.

One cycle of PEALD SiO2 consists of 3 steps: chemisorption of an aminosilane precursor on the substrate, purging the precursor by inert gas flow, and plasma-assisted surface reaction of chemisorbed precursor with reactant gas. The RF-based plasma pulse is <400ms in length. Growth per cycle (GPC) of PEALD SiO2 increases with decreasing deposition temperature [6]. This GPC temperature dependence indicates the ALD reaction is limited by the desorption rate of the physisorbed precursor, which increases with increasing deposition temperature. Because this is an ALD process, film thickness is proportional to cycle number and thickness can be precisely controlled. These PEALD films have been confirmed to not cause plasma damage to the underlying substrate/films as the RF power during the deposition process is much smaller (<50W) than that of conventional PECVD.

Figure 3. PEALD SiO2 deposition on resist at 50ºC.

As shown in Fig. 3a, 300Å of a conformal SiO2 film can be deposited directly on resist at 50°C without any damage. Furthermore, in situ treatments can be used to widen the space between lines and/or reform the resist shape. Figure 3b shows an example of in situ treatment before SiO2 deposition. In this case, the resist is slimmed isotropically by ~65Å. Within wafer uniformity of the treatment process is typically <2%, 3σ. This is a good example showing the process flexibility gained by using a mini-batch system, while sustaining the high throughputs required for manufacturing.


Overcoming the initial barriers to adoption has required the creation of several toolset configurations to address the unique issues in specific applications. Single-wafer, batch and mini-batch ALD solutions are available, each with thermal and plasma enhanced capabilities, and selection of the appropriate manufacturing toolset is as critical to eventual technology adoption as the process itself. In very cost sensitive markets such as memories, cost-of-ownership (COO) will be a main driver for equipment selection. In foundry or other logic applications, equipment choice is more a mix between COO, turn-around time and process performance considerations and choices of equipment type have to be made with careful regard to the specific application.


1. C. Goodman, et al., “Atomic Layer Epitaxy,” Jour. of Appl. Physics, R65-R81, 1986.

2. D. Triyoso, et al., “Physical and Electrical Characteristics of Atomic-Layer-Deposited Hafnium Oxide Formed Using Hafnium Tetrachloride and Tetrakis(ethylmethylaminohafnium),” Jour. of Appl. Physics, Vol. 97, 124107, 2005.

3. H. P. W. Hey et. al., “Ion Bombardment: A Determining Factor in Plasma CVD,” Solid State Technology, pp. 139-144, April, 1990.

4 . L. Niinistö, et. al., “Advanced Electronic and Optoelectronic Materials by Atomic Layer Deposition: An Overview with Special Emphasis on Recent Progress in Processing of High-k Dielectrics and Other Oxide Materials,” Physica Status Solidi (a), 201, p. 1443–1452, 2004

5. E. Granneman, et al., Batch ALD: Characteristics, Comparison with Single-wafer ALD, and Examples, Surface and Coatings Technology, Vol. 201, p. 8899 – 8907, 2007.

6 . A. Kobayashi, et al., Temperature Dependence of GPC with PEALD-SiO,” Proc. 10th Inter. Conf. on Atomic Layer Deposition, p. 31, 2010.


Mohith Verghese earned a BS in chemical engineering from the U. of Texas at Austin and a MS in chemical engineering from the U. of Arizona. He is technical product manager of ALD technologies at ASM America, Phoenix, AZ, USA; ph: +1-602-470-2736, email:  [email protected]

Jan Willem Maes received his PhD in applied physics from Delft U. of Technology and works at ASM Belgium on ALD and EPI process application development projects.

Nobuyoshi Kobayashi earned a BS, a MS, and a PhD in solid state physics from the U. of Tokyo. He is director of PECVD and PEALD technologies at ASM Japan, Tama in Tokyo.

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