Category Archives: Etch


Lam Research Corp. (Nasdaq: LRCX), an advanced manufacturer of semiconductor equipment, today announced that it is expanding its atomic layer etching (ALE) portfolio with the addition of ALE capability on its Flex dielectric etch systems. Enabled by Lam’s Advanced Mixed Mode Pulsing (AMMP) technology, the new ALE process has demonstrated the atomic-level control needed to address key challenges in scaling logic devices to 10nm and below. First in the industry to use plasma-enhanced ALE in production for dielectric films, the latest Flex system has been adopted as tool of record for high-volume manufacturing of logic devices.

“From transistor and contact creation to interconnect patterning, a new level of precision is needed by logic manufacturers to continue scaling beyond the 10nm technology node,” said Vahid Vahedi, group vice president, Etch Product Group. “For device-enabling applications like self-aligned contacts, where etch helps create critical structures, conventional technologies do not provide sufficient control for the stringent specifications now demanded. Our latest Flex product with dielectric ALE delivers atomic-scale control with proven productivity to meet customers’ key requirements.”

To continue logic device scaling, chipmakers are adopting new integration schemes such as those using self-aligned contacts (SACs) in order to address issues like RC delay. As a result, contact etch has become one of the most crucial processes, directly impacting both wafer yield and transistor performance. In order to define critical device structures with high fidelity, the etch process requires directional (anisotropic) capability with ultra-high selectivity, while also delivering the productivity needed for manufacturing.

For next-generation logic and foundry applications, Lam’s Flex dielectric etch systems offer the industry’s most advanced capacitively coupled plasma (CCP) reactor, featuring a unique, small-volume design to deliver repeatable results. The latest system uses proprietary AMMP technology to enable ALE of dielectric films such as silicon dioxide (SiO2). This capability results in a 2x improvement in selectivity over previous dielectric etch technologies while delivering atomic-level control.


January 6, 2016

The process of creating a pattern on a wafer is known as lithography. Typically, light is shone through a mask onto a photoresist that coats the wafer. After exposure, the photoresist is “developed,” which removes the exposed part of the resist (or the unexposed resist if it is negative resist). A photoresist coat/bake/develop system — often called a “track system” is typically connected directly to the wafer exposure tool or wafer “stepper.”

The exposed wafer is then etched, where the photoresist acts as a barrier to the etching chemicals or reaction ions. The photoresist is then removed by stripping or “ashing.” In complex integrated circuits, a modern CMOS wafer will go through the photolithographic cycle up to 50 times, making lithography one most critical process step.

Increasingly smaller wavelengths of light have been used to create smaller dimensions. Complex mask designs have also evolved, such as optical proximity correction (OPC), to correct for optical effects. Mask-source optimization techniques have also been developed to correct for variations in the source and on the wafer.

A push to extreme ultra-violet (EUV) lithography has been under way for a decade or more, led by ASML Lithography. Alternatives have also been research and developed, including nano-imprint lithography (NIL), which uses stencils and multi e-beam (MEB) lithography, which uses a large bank of individually controlled electron beams to expose the wafer directly (no mask required). More recently, an interesting approach called directed self-assembly (DSA) has been studied, which enables very small dimensions. DSA uses a guide structure on the wafer and polymer-based chemicals to create regular lines with very small dimensions.

Check out our Lithography Topic Center for regular updates.

Additional Reading:

Feed-forward overlay control in lithography processes using CGS

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

ORBOTECH LTD. today announced that SPTS Technologies, an Orbotech company and a supplier of advanced wafer processing solutions for the global semiconductor and related industries, has supplied CEA-Leti, one of Europe’s largest micro- and nanotechnologies research institutes, with its vapor HF etch release systems for 300mm microelectromechanical systems (MEMS) on CMOS development. Installed in 2015 at CEA-Leti’s facility in Grenoble, France, the Monarch300 joins the 200 and 300mm etch, CVD and PVD systems previously supplied by SPTS and which are already operational in CEA-Leti’s MEMS and packaging lines.

“The co-integration of MEMS and CMOS has the potential to create a new family of sensors with improved performance,” said Kevin Crofton, President of SPTS and Corporate Vice President at Orbotech. “The Monarch 300 uses our patented Primaxx vapor HF etch technology and is capable of processing thirteen 300mm wafers simultaneously. NEMS and MEMS are at the core of CEA-Leti’s activities, and we are pleased to be able to supply this highly valued partner with additional capability to support its 300mm MEMS program.”

Marie-Noëlle Semeria, CEO of Leti and President of the Nanoelec RTI board, commented: “MEMS devices co-integrated with CMOS help Leti achieve a long-standing goal of enabling smaller and more powerful sensors and actuators, without exceeding power budgets.”

“After characterizing the performance of a number of competing vapor HF etch methodologies, we selected SPTS’ Primaxx reduced-pressure, dry technology because it extends our existing process capability significantly and offers enhanced compatibility with materials of interest. Leti intends to lead the way in developing MEMS devices on 300mm formats, and to achieve this we are partnering with industry leaders such as SPTS, who have the specialist process knowledge needed to transfer our 300mm MEMS developments to high-volume production,” added Fabrice Geiger, Head of the Silicon Technologies Division of CEA-Leti.

SPTS and CEA-Leti entered into a two-year agreement that will encompass full performance characterization and process optimization of both the 200mm and 300mm vapor HF process modules. This collaboration will further extend the long-standing relationship between these partners who already collaborate on the development and optimization of a range of etch and deposition processes for next-generation 3D high-aspect-ratio through-silicon-via (TSV) solutions.


December 11, 2015

“Dry” (plasma) etching is used for circuit-defining steps, while “wet” etching (using chemical baths) is used mainly to clean wafers. Dry etching is one of the most frequently used processes in semiconductor manufacturing. Before etching begins, a wafer is coated with photoresist or a hard mask (usually oxide or nitride) and exposed to a circuit pattern during photolithography. Etching removes material only from the pattern traces. This sequence of patterning and etching is repeated multiple times during the chip making process.

Etch processes are referred to as conductor etch, dielectric etch, or polysilicon etch to indicate the types of films they are remove from the wafer. For example, dielectric etch is involved when an oxide layer is etched to leave “oxide isolators” separating devices from each other; polysilicon etch is used to create the gate in a transistor; dielectric etch is employed to etch via holes and trenches for metal conductive paths; and metal etch removes aluminum, tungsten, or copper layers to reveal the pattern of circuitry at progressively higher levels of the device structure.

Plasma etching is performed by applying electromagnetic energy [typically radio frequency (RF)] to a gas containing a chemically reactive element, such as fluorine or chlorine. The plasma releases positively charged ions that bombard the wafer to remove (etch) materials and chemically reactive free radicals that react with the etched material to form volatile or nonvolatile byproducts. The electric charge of the ions directs them vertically toward the wafer. This produces the almost vertical etch profiles essential for the miniscule features in today’s densely packed chip designs. Typically, high etch rates (amount of material removed in a given time) are desirable.

Process chemistries differ depending on the types of films to be etched. Those used in dielectric etch applications are typically fluorine-based. Silicon and metal etch use chlorine-based chemistries. A specific etch step may be performed on one or more film layers. When multiple layers are involved and also when the etch process must stop precisely on a particular layer without damaging it, the selectivity of the process becomes important. Selectivity is the ratio of two etch rates: the rate for the layer to be removed and the rate for the layer to be protected (e.g. mask or stop layer). Higher selectivities are usually desirable.

In reactive ion etching (RIE), described above, the objective is to optimize the balance between physical and chemical etching such that physical bombardment (etch rate) is sufficient to remove the requisite material while appropriate chemical reactions occur to form either easily exhausted volatile byproducts or protective deposits on the remainder (selectivity and profile control). Magnetically enhanced RIE can aid processing by increasing ion density without increasing ion energy (which can damage the wafer).

Ideally, the etch rate is the same (uniform) at all points on a wafer. The degree to which it might vary at different points on the wafer is known as non-uniformity (or microloading) and is usually expressed as a percentage. Minimizing non-uniformity and microloading are important objectives in etching.

Source: Applied Materials

Additional Reading

Moving atomic layer etch from lab to fab

Applied Materials, Inc. today announced a next-generation etch tool, the Applied Centris Sym3 Etch system, featuring an entirely new chamber for atomic-level precision manufacturing. To overcome within-chip feature variations, the Centris Sym3 system leapfrogs current tools to provide chipmakers with the control and precision needed to pattern and create densely packed 3D structures in advanced memory and logic chips.

“Drawing on over 20 years of etch learning and our expertise in precision materials removal, the Sym3 system represents a brand new design, built from the ground up, that solves persistent and impending industry challenges,” said Dr. Raman Achutharaman, vice president and general manager of Applied’s Etch business unit. “Customer traction has been remarkable, resulting in the fastest adoption rate we’ve seen for an etch tool in the company’s history, with record ramp to production at leading-edge fabs.”

The Centris Sym3 etch chamber employs Applied’s True Symmetry technology with multiple tuning controls for optimizing global process uniformity to the atomic level. Key to the design is a focus on controlling and removing etch byproducts, which are increasingly hampering within-chip patterning uniformity. The system mitigates byproduct re-deposition to overcome the challenges of line edge roughness, pattern loading and defects – issues that are becoming more limiting for each successive technology node. Combined with an advanced RF technology that controls ion energy and angular distributions, the Sym3 system delivers unsurpassed vertical profiles for high aspect ratio 3D structures.

The Centris Sym3 platform’s six etch and two plasma clean process chambers feature system intelligence software to ensure that every process in every chamber matches precisely, enabling repeatability and high productivity for high-volume manufacturing. 

Applied Materials, Inc. develops engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries. 

By Jeff Dorsch, Contributing Editor

Plasma etching is a key step in wafer fabrication, from deposition to the patterning of photolithography to dry or wet etch. As such, it is a crucial and hotly-contested area for vendors of semiconductor manufacturing equipment.

Lam Research holds about half of the worldwide etch equipment market and principally competes with Applied Materials, Tokyo Electron, and Hitachi High-Technologies.

In May, Lam introduced the Kiyo F Series conductor etch system for volume production of advanced DRAMs and 3D NAND flash memory devices. Lam says the Kiyo F Series is employed for critical conductor etch applications at “all major memory manufacturers.”

A year ago, Lam brought out the 2300 Kiyo F Series with the Hydra Uniformity System, which corrects for critical-dimension non-uniformities on the incoming wafer. The company also unveiled an atomic layer etch (ALE) capability on the 2300 Kiyo F Series conductor etch system, which is paired with Lam’s atomic layer deposition (ALD) systems, the VECTOR ALD Oxide system for dielectric film ALD and the ALTUS system for tungsten metal film ALD.

Applied Materials and Tokyo Electron set plans in 2013 to merge their companies. The merged company, to be called Eteris, would have commanded about one-third of the worldwide etching equipment market. The merger was called off in April, however, as U.S. antitrust regulators indicated that they would not approve the transaction.

SEMI cheered a decision by the U.S. Department of Commerce in February to remove export controls on certain etch equipment, concluding a four-month investigation. SEMI had petitioned the federal government agency in July 2014 to look at the foreign availability of anisotropic plasma dry etching equipment.

“SEMI stands for free trade and open markets to support the development and success of the global semiconductor manufacturing industry supply chain,” Denny McGuirk, president and CEO of SEMI, said in a statement. “We applaud the decontrol of semiconductor etch equipment as a rational response to current technology, trade, and commercial realities. This is a win for both equipment makers and their customers operating in the global market.”

“The Commerce Department’s decision to remove export control restrictions for etch equipment is a big victory for the U.S. semiconductor equipment sector and our customers around the world,” said Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials. “Recognizing the availability of these tools will help fuel growth and promote the success of the global industry supply chain.”

In May, imec and Tokyo Electron presented a direct copper etch scheme for patterning copper interconnections. This would replace the usual copper damascene process, according to imec and TEL. The Belgian research organization worked with nine leading chipmakers on developing the direct copper etch technology.

Dry or wet, etching technology will be the subject of discussions at the SEMICON West 2015 conference and exhibition.

Applied Materials today announced the Applied Centura Tetra Z Photomask Etch system for etching next-generation optical lithographic photomasks needed by the industry to continue multiple patterning scaling to the 10nm node and beyond. The new tool extends the capabilities of Applied’s Tetra platform, delivering angstrom-level photomask accuracy for critical dimension (CD) parameters required to meet stringent patterning specifications for future logic and memory devices.

“Our Tetra Z system represents the state of the art in photomask etch technology, employing advances in precision materials engineering and plasma reaction kinetics to extend the use of 193nm lithography,” said Rao Yalamanchili, general manager of Applied’s Mask Etch product division. “Using the 193nm wavelength to produce 10nm or 7nm patterns requires a range of optimization techniques, including immersion and multiple patterning, which rely heavily on photomasks. Etch technology is key for photomask fabrication; the Tetra Z system is unique in delivering the accuracy required to etch next-generation optical photomasks for patterning advanced node designs.”

Applied developed the Tetra Z tool for advanced chrome, molybdenum silicon oxynitride (MoSi), hard mask and quartz (fused silica) etch applications used to fabricate advanced binary and phase-shift masks (PSMs). Offering continuous technical innovations and unprecedented CD performance, the system extends immersion lithography for quadruple patterning and cutting-edge resolution enhancement techniques. Vital capabilities ensuring pattern transfer fidelity include uniform, linear precision etching across all feature sizes and pattern densities with virtually zero defectivity.

Excellent CD performance combined with high etch selectivity enable the use of thinner resist films for achieving smaller photomask CD patterns on critical device layers. Controllable CD bias capability expands the system’s flexibility to meet customer specific requirements. Unique quartz etch depth control ensures precision phase angle and aids integrated circuit scaling by providing customers the capability to use alternating aperture PSMs and chromeless phase lithography. These key advances derive from a variety of system improvements in chamber design, plasma stability, ion and radical control, flow and pressure control, and real-time process monitoring and control.

Applied’s Tetra systems have been selected by a majority of mask makers worldwide to etch high-end photomasks over the past decade.

Applied Materials, Inc. is a developer of precision materials engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries.

centura tetra z