Category Archives: Resist Stripping



January 6, 2016

The process of creating a pattern on a wafer is known as lithography. Typically, light is shone through a mask onto a photoresist that coats the wafer. After exposure, the photoresist is “developed,” which removes the exposed part of the resist (or the unexposed resist if it is negative resist). A photoresist coat/bake/develop system — often called a “track system” is typically connected directly to the wafer exposure tool or wafer “stepper.”

The exposed wafer is then etched, where the photoresist acts as a barrier to the etching chemicals or reaction ions. The photoresist is then removed by stripping or “ashing.” In complex integrated circuits, a modern CMOS wafer will go through the photolithographic cycle up to 50 times, making lithography one most critical process step.

Increasingly smaller wavelengths of light have been used to create smaller dimensions. Complex mask designs have also evolved, such as optical proximity correction (OPC), to correct for optical effects. Mask-source optimization techniques have also been developed to correct for variations in the source and on the wafer.

A push to extreme ultra-violet (EUV) lithography has been under way for a decade or more, led by ASML Lithography. Alternatives have also been research and developed, including nano-imprint lithography (NIL), which uses stencils and multi e-beam (MEB) lithography, which uses a large bank of individually controlled electron beams to expose the wafer directly (no mask required). More recently, an interesting approach called directed self-assembly (DSA) has been studied, which enables very small dimensions. DSA uses a guide structure on the wafer and polymer-based chemicals to create regular lines with very small dimensions.

Check out our Lithography Topic Center for regular updates.

Additional Reading:

Feed-forward overlay control in lithography processes using CGS

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

By Jeff Dorsch, Contributing Editor

Plasma etching is a key step in wafer fabrication, from deposition to the patterning of photolithography to dry or wet etch. As such, it is a crucial and hotly-contested area for vendors of semiconductor manufacturing equipment.

Lam Research holds about half of the worldwide etch equipment market and principally competes with Applied Materials, Tokyo Electron, and Hitachi High-Technologies.

In May, Lam introduced the Kiyo F Series conductor etch system for volume production of advanced DRAMs and 3D NAND flash memory devices. Lam says the Kiyo F Series is employed for critical conductor etch applications at “all major memory manufacturers.”

A year ago, Lam brought out the 2300 Kiyo F Series with the Hydra Uniformity System, which corrects for critical-dimension non-uniformities on the incoming wafer. The company also unveiled an atomic layer etch (ALE) capability on the 2300 Kiyo F Series conductor etch system, which is paired with Lam’s atomic layer deposition (ALD) systems, the VECTOR ALD Oxide system for dielectric film ALD and the ALTUS system for tungsten metal film ALD.

Applied Materials and Tokyo Electron set plans in 2013 to merge their companies. The merged company, to be called Eteris, would have commanded about one-third of the worldwide etching equipment market. The merger was called off in April, however, as U.S. antitrust regulators indicated that they would not approve the transaction.

SEMI cheered a decision by the U.S. Department of Commerce in February to remove export controls on certain etch equipment, concluding a four-month investigation. SEMI had petitioned the federal government agency in July 2014 to look at the foreign availability of anisotropic plasma dry etching equipment.

“SEMI stands for free trade and open markets to support the development and success of the global semiconductor manufacturing industry supply chain,” Denny McGuirk, president and CEO of SEMI, said in a statement. “We applaud the decontrol of semiconductor etch equipment as a rational response to current technology, trade, and commercial realities. This is a win for both equipment makers and their customers operating in the global market.”

“The Commerce Department’s decision to remove export control restrictions for etch equipment is a big victory for the U.S. semiconductor equipment sector and our customers around the world,” said Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials. “Recognizing the availability of these tools will help fuel growth and promote the success of the global industry supply chain.”

In May, imec and Tokyo Electron presented a direct copper etch scheme for patterning copper interconnections. This would replace the usual copper damascene process, according to imec and TEL. The Belgian research organization worked with nine leading chipmakers on developing the direct copper etch technology.

Dry or wet, etching technology will be the subject of discussions at the SEMICON West 2015 conference and exhibition.