Category Archives: Wafer Annealing

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Ion Implantation

December 11, 2015

Ion implantation is a materials engineering process by which ions of a material are accelerated in an electrical field and directed into the wafer, typically to form the source and drain regions of the transistor.

Ion implantation equipment typically consists of an ion source, where ions of the desired element are produced, an accelerator, where the ions are electrostatically accelerated to a high energy, and a target chamber, where the ions impinge on a target, which is the material to be implanted. Thus ion implantation is a special case of particle radiation. Each ion is typically a single atom or molecule, and thus the actual amount of material implanted in the target is the integral over time of the ion current. This amount is called the dose. The currents supplied by implanters are typically small (microamperes), and thus the dose which can be implanted in a reasonable amount of time is small. Therefore, ion implantation finds application in cases where the amount of chemical change required is small.

Typical ion energies are in the range of 10 to 500 keV (1,600 to 80,000 aJ). Energies in the range 1 to 10 keV (160 to 1,600 aJ) can be used, but result in a penetration of only a few nanometers or less. Energies lower than this result in very little damage to the target, and fall under the designation ion beam deposition. Higher energies can also be used: accelerators capable of 5 MeV are common. However, there is often great structural damage to the target, and because the depth distribution is broad, the net composition change at any point in the target will be small.

The energy of the ions, as well as the ion species and the composition of the target determine the depth of penetration of the ions in the solid: A monoenergetic ion beam will generally have a broad depth distribution. The average penetration depth is called the range of the ions. Under typical circumstances ion ranges will be between 10 nanometers and 1 micrometer.

Accelerator systems for ion implantation are generally classified into medium current (ion beam currents between 10 μA and ~2 mA), high current (ion beam currents up to ~30 mA), high energy (ion energies above 200 keV and up to 10 MeV), and very high dose (efficient implant of dose greater than 1016 ions/cm²).

Dopant ions such as boron, phosphorus or arsenic are generally created from a gas source, so that the purity of the source can be very high.

One prominent method for preparing silicon on insulator (SOI) substrates from conventional silicon substrates is the SIMOX (separation by implantation of oxygen) process, wherein a buried high dose oxygen implant is converted to silicon oxide by a high temperature annealing process.

Suppliers of ion implanters include Applied Materials, Axcelis and High Energy Corp.

Additional Reading

Leveraging ion implant process characteristics to facilitate 22nm devices

Threshold voltage tuning for 10nm and beyond CMOS integration

How to verify incident implant angles on medium current implants

Laser spike annealing resolves sub-20nm logic device manufacturing challenges

December 18, 2014

LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices.

By YUN WANG, Ph.D., Ultratech, San Jose, CA

Sub-20nm system-on-chip and FinFET devices have specific manufacturing challenges that can be resolved with laser spike annealing (LSA) technology. Over the last decade, new process technologies and materials have emerged, such as strained silicon, high-k/metal gate (HKMG) and advanced silicide. Meanwhile transistor structures have evolved significantly, from bulk planar and PDSOI to 3D FinFET. With dimensions approaching atomic scales, the need for low thermal budget processes offered by millisecond annealing (MSA) becomes more important to precisely control the impurity profiles and engineer interfaces. This article will explain how LSA technology plays an enabling role to overcoming manufacturing challenges for sub-20nm logic devices.

LSA and MSA

The European semiconductor equipment market is expected to grow along with the world market. Global capital spending on semiconductor equipment is projected to grow 21.1 percent in 2014 and 21.0 percent in 2015. According to the August edition of the SEMI World Fab Forecast, semiconductor equipment spending will increase from $29 billion in 2013 to $42 billion in 2015.

In this article the terms LSA and MSA are used interchangeably. MSA can be implemented either by a scanning laser or a bank of flash lamps (FIGURE 1). In both cases, a reduced volume of substrate is heated to high temperature by a powerful light source, which results in fast temperature ramping compared to conventional RTP. Surface cooling in the millisecond time scale is dominated by conductive heat dissipation through the lower temperature substrate, which is several orders of magnitude faster than radiation heat loss or convection cooling through surfaces. The wafer backside is typically heated by a hot chuck or lamps to reduce the front surface peak temperature jump, and in some cases, to reduce the flash lamp power requirement or facilitate laser light absorption. Flash usually requires higher backside heating temperature than the laser option.

FIGURE 1. Simulated temperature distribution in silicon substrate by millisecond nonmelt scanning laser (left) and flash lamp heating (right).

There are important differences between flash and laser approaches. The flash system provides global heating where the top surface of the entire wafer is heated at the same time. Hence heat dissipation occurs only in one dimension (1D – vertical direction). In addition, the backside needs to be floated to relieve the stress caused by global wafer bending due to the vertical thermal gradient. The laser system, on the other hand, provides localized heating around the scanning beam. The heat dissipation is between two-dimensional (2D) and three-dimensional (3D) (2D for an infinitely long line beam, and 3D for a point source). Since the thermal stress is localized, the backside can be chucked to facilitate heat sinking.

The difference in heat dissipation has a significant impact on the cooling rate, in particular, when long annealing or high intermediate (preheat) temperature is used. FIGURE 2 compares the temperature (T) profiles between laser and flash systems for the same peak surface temperature (Tpk) and dwell time (tdwell— defined as the full-width-half-maximum duration when a fixed point on the wafer sees the laser beam or flash pulse). The latter shows much slower ramp down. This is because once the flash energy is dissipated through the wafer thickness, the cooling is limited by the same radiation loss mechanism as in RTP. For applications relying on non-equilibrium dopant activation, the extra thermal budget due to the slow ramp down could be a concern for deactivation.

FIGURE 2. Comparison of simulated temperature profiles between long dwell laser and flash annealing. Tpk = 1200°C, dwell time = 10ms, preheat T = 800°C for flash. Inset shows details magnified around peak temperature.

LSA technology uses a long wavelength p-polarized CO2 laser with Brewster angle incidence. Previous studies have shown that such configuration has benefits of reduced pattern density effect compared to short wavelength with near normal incidence. A second beam can be added to form a dual beam system that allows more flexibility to adjust the temperature profiles, and expands the process capability to low T and long dwell time.

FIGURE 3 shows different LSA annealing temperature-time (T-t) regimes that can be used to meet various application needs. Standard LSA used in front-end applications has Tpk ranging from 1050~1350°C and tdwell from 0.2~2ms. Short dwell time is beneficial for reducing wafer warpage and litho misalignment, especially for devices with high strain. Long dwell time (2~40ms) adds more thermal budget for defect curing. It can also be used to improve activation and fine tune the junction depth. The low T regime enables applications that require lower substrate and peak annealing temperatures, such as annealing of advanced silicide or new channel/gate stack materials that have poor thermal stability.

FIGURE 3. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

High-k/metal gate (HKMG)

The impact of MSA on HKMG is thinner equivalent oxide thickness (EOT) due to reduced interfacial layer growth from a lower thermal budget. Lower leakage and better surface morphology are also observed in hafnium-based, high-k films when annealed by a laser.

Incorporating nitrogen into a high-k dielectric film can improve thermal stability, reliability, and EOT scaling. Post nitridation anneal with MSA provides opportunities to stabilize the film with a more precisely controlled nitrogen profile, which is important since excessive nitrogen diffusion can increase interface trap and leakage. Oxygen has a strong impact on the characteristics of HKMG and it is important to control the ambient environment during the gate annealing. Full ambient control capability has been developed for LSA to accommodate this need. FIGURE 4 shows the schematics of our patented micro-chamber approach that allows ambient control to be implemented in a scanning system using non-contact gas bearing. Different process gas can be introduced to accommodate various annealing and material engineering needs.

FIGURE 4. LSA extended process space. For comparison, T-t regimes of conventional RTA and nanosecond melt laser annealing are also shown.

Advanced silicide

Conventional NiSi processing involves two RTA steps. The 1st RTA (200~300°C) forms Ni-rich silicide, and the 2nd RTA (400~500°C) after selective etch of un-reacted Ni forms the desired low resistance NiSi phase. By replacing the 2nd RTA with a high temperature MSA (700~900°C), it can reduce leakage as well as improve performance. The improvement in leakage distribution results from the statistical reduction of Ni pipe defects due to the low thermal budget of MSA.

High temperature promotes phase mixing of Si-rich Ni silicide at the silicide/Si interface and lowers Schottky barrier height (SBH). In conventional RTA, this requires T > 750°C; such high T would lead to morphology degradation, excess diffusion, and higher resistivity. With MSA, because of the short duration, agglomeration does not occur until ~900°C.

To maximize the performance gain, anneal at high T close to the agglomeration threshold is desired. In such a case, minimizing within-die pattern effects and implementing within-wafer and wafer to-wafer temperature control becomes very important.

FinFETs

As FinFETs shrink, interface contact resistance, Rc, becomes more critical (FIGURE 5). A promising path to lower Rc is interface engineering by dopant segregation using pre or post silicide implantation.

FIGURE 5. Parasitic resistance components for different nodes of FinFET, calculated using an analytical model. of 10-8 -cm2 is used.

FIGURE 6. SIMS profiles of Ga-doped (left) p+/n and As-doped (right) n+/p Ge junctions annealed by LSA. For Ga, no diffusion is observed. For As, concentration enhanced diffusion is observed but can be reduced with short dwell time.

Thermal annealing is necessary to repair implant damage and activate dopants in pre silicide implantation scheme, and to drive-in dopants in post silicide case. Using MSA instead of RTA results in more precise dopant profile control, higher dopant concentration at the interface and less potential silicide defectivity, due to the lower thermal budget.

Recently, Ti re-emerged as an option for contact metal because of better thermal stability and potential lower SBH. LSA can be applied to form low Rc Ti/Si contact. In advanced FinFET flow where contacts are formed after source/drain activation and gate stack, low thermal budget process is beneficial to minimize dopant deactivation and unintentional gate work function shift.

In-situ doped selective epitaxial growth is increasingly used to form the raised source/drain for FinFET. There is, however, a limitation in the maximum activation level it can achieve. Activation can be improved using MSA in combination with additional implantation. Drastic FinFET performance improvement has been achieved with co-optimization of conformal doping, selective epitaxial growth, implantation and MSA. In addition to front-end and middle-of-line applications, there are also opportunities at the back-end. One example is low-k curing. For FinFET, low-k is important not only as an inter-Cu dielectric, but also as a transistor-level dielectric to minimize the parasitic capacitance arising from 3D topography. The modulus and hardness of the low-k films can be improved without adversely impacting the k value using MSA.

New channel materials

Below the 10nm technology node, new materials with enhanced transportation, such as SiGe/Ge and III-V compounds, may be needed to meet the performance requirements. These materials have low thermal stability and are lattice mis-matched with the Si substrate, as a result physical integrity during thermal annealing is a very big concern. Low thermal budget processing by MSA provides a way to alleviate this issue. For example, studies on SiGe/Si heterostructures have shown that MSA can enable a higher annealing temperature than RTA, without strain relaxation or structural degradation. This results in improved activation. With MSA, junctions with enhanced activation and reduced diffusion can be obtained.

Summary

We have reviewed various applications of millisecond annealing for advanced device fabrication. As new materials emerge and device dimensions approach the atomic scale, precise thermal budget control becomes critical. This opens new opportunities for short time scale annealing. In addition to the traditional dopant activation and impurity profile control, MSA can also be used for interface engineering and material property modifications (structural, electrical, chemical, and mechanical). In general, if a desired process has higher thermal activation energy than an undesired process, application of high temperature, short duration annealing is beneficial.

YUN WANG, Ph.D., is Senior Vice President and Chief Technologist of Laser Processing Ultratech, San Jose, CA.

Threshold voltage tuning for 10nm and beyond CMOS integration

October 13, 2014

A novel metal gate integration scheme to achieve precise threshold voltage (VT) control for multiple VTs is described.

BY NAOMI YOSHIDA, KEPING HAN, MATTHEW BEACH, XINLIANG LU, RAYMOND HUNG, HAO CHEN, WEI TANG, YU LEI, JING ZHOU, MIAO JIN, KUN XU, ANUP PHATAK, SHIYU SUN, SAJJAD HASSAN, SRINIVAS GANDIKOTA, CHORNG-PING CHANG and ADAM BRAND, Applied Materials, Santa Clara, CA

At very small process geometries, precise control of electrical conductivity is difficult to maintain. The industry requires a viable replacement-gate FinFET architecture to continue scaling high performance CMOS [1, 2] technology and designs. Furthermore, cost-effective and precise VT control to achieve multiple VTs is essential for future ULSI fabrication to achieve optimal power consumption and performance.

In this study, using WFM full fill and combining two techniques — the novel metal composition and ion implantation into the WFM process, we successfully realized three critical aspects for the metal gate for 10 nanometer and beyond. These are: 1) precise effective work function (eWF) control over a 600 millivolt (mV) tuning range to achieve multiple VT, 2) maintaining conductivity for a sub-15 nanometer gate trench, and 3) compatibility to the self-aligned contact (SAC).

A metal oxide semiconductor capacitor (MOSCAP) was used to evaluate the impact of the metal compo- sition and beam line ion implantation on eWF. Ion implantation was performed for some of the samples after high-k dielectric and work function metal deposition on blanket wafers. High frequency capacitance voltage (HFCV) and current voltage (IV) measurements were recorded for the MOSCAP samples. A single damascene structure was used to measure sub-20 nanometer line resistance. A planar MOSFET was also used for evaluating impact on VT and variability.

Work function modulation

FIGURE 1 shows eWF with three compositions of NMOS WF metals (nWFM) compared with RF-PVD titanium aluminum (TiAl) that was used as the nWFM reference metal. Results demon- strated that the difference between the highest and lowest WF was 550 mV and is attributed to the ALD TiAl composition. Nitrogen ion implantation into the ALD TiAl enabled further WF tuning by 100-150 mV steps. This made possible a WF range from near the Si conduction band edge of 4.1 electron volts (eV) for NMOS low VT to above mid-gap 4.7 eV. The WF shift corresponded well to the different dose levels; therefore we demonstrated that ion implantation can be used to pinpoint the target WF. In addition, we found that ion implantation into ALD TiAl does not degrade the gate leakage current and effective oxide thickness (EOT) performance.

FIGURE 1. nWFM composition impact on eWF.

Maintaining metal gate conductance for 10nm node

According to the ITRS roadmap, a gate length of 17 nanometers is expected for the 10 nanometer technology node [3]. The problem is that after the high-k cap and etch stop depositions, the gate will have limited space left for the metal fill process [4]. One solution is to fully or mostly fill the trench with WF metal. Using an advanced ALD TiAl deposition process, we were able to fill 13 nanometer wide trenches without any gapfill voids. FIGURE 2 shows the extendible conductance of the ALD TiAl and WF fill process.

FIGURE 2. Conductance curves of various metals filling small trenches.

It is known that NMOS low WF metals are more prone to oxidization than high WF PMOS films such as titanium nitride (TiN) and that air exposure affects VT control [5]. In our study, degradation on the conductance curves from air exposure was also observed (FIGURE 3). The air exposed sample showed a large offset of the conductance curve to the right while maintaining the slope, i.e. differential resistivity. The TEM (FIGURE 4) shows an additional layer between the TiN barrier and ALD TiAl. Scanning transmission electron microscope- electron energy loss spectroscopy analysis confirmed high oxygen in the white interface. Thus, it is critical to have an in situ ALD TiAl process on the high k TiN cap to maintain conductivity for the 10 nanometer node.

FIGURE 3. Effect of air exposure in between TiN barrier and nWF metal on conductance below 30 nanometers.

FIGURE 4. TEM images at interface of TiN barrier and nWFM. The ex situ sample shows oxidized interface by air exposure.

Self-aligned contact compatibility and CMOS VT tuning

At the 22 nanometer technology node, a metal gate SAC is necessary to scale contacted gate pitch [1]. This requires a well-controlled etch back of the metal gate, with subsequent capping of the etch stop material such as silicon nitride (SiN) to prevent contact to gate shorts. Tungsten (W) has been used in volume production because it offers a robust etch back process. In our study, we demonstrated that a controlled recess etch can be achieved with the more conductive TiAl fill compared to W (FIGURE 5). In addition, after metal etch back, a SAC cap was successfully formed with a high density plasma (HDP) SiN fill and chemical mechanical planarization (CMP).

FIGURE 5. Cross-sectional TEM images show controlled etch back of ALD TiAl fill metal gate for SAC integration. The left and middle images after recess etch-back. The right image is after Cap Nitride CMP.

Multiple WF metals need to be integrated for CMOS VT tuning for NMOS and PMOS. In our study we examined the CMOS ALD TiAl flow for four VT tunings. From the results, we propose a new process flow: 1) after the high-k and etch stop layer deposition steps, a fully clustered barrier TiN and nWFM be deposited. Some areas can be masked by photoresist (PR) and the exposed area modified by ion implantation. 2) Etch off the first nWF layer from the PMOS areas. 3) Deposit the second WF (N-3) and barrier. 4) Perform second ion implantation to shift the WF of the third device. 5) Lastly, ALD TiAl is again etched off from the PMOS area WFM (TiN), followed by W or Al fill to fill the remaining gap. The last TiN material serves as the highest WF as well as the barrier layer for W or Al. This flow provides four VTs and metal fill with a clustered nWFM film stack.

Conclusion

Metal WF modulation for VT tuning using a new scheme tunable in the range of 600 mV was successfully demonstrated for 10 nanometer CMOS integration. Ion implantation dose control enabled continuous WF tuning for multiple VT targets. Metal gate conductance data showed the benefit of in situ processing with a TiN barrier and NMOS WF metal. Based on the results, a CMOS flow with NMOS WF-first was proposed for multi-VT tuning.

References

1. C. Auth et al., VLSI Tech. Sym. Dig., p. 131, (2012)
2. P. Packan et al., IEDM Tech. Dig., p. 659, (2009)
3. ITRS Roadmap 2011 Edition
4. N. Yoshida, et al., VLSI Tech. Sym. Dig., p. 81, (2012) 5. A. Veloso, et al., VLSI Tech. Sym. Dig., p. 33, (2012)

How to verify incident implant angles on medium current implants

October 30, 2013

BOBBY ISAACS and ANYA CORNELL, Texas Instruments, Dallas, Tex.

Results can depend on the properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique.

Semiconductor chip geometries continue to shrink, causing once unimportant parameters in the manufacturing process to become more critical. With the shrinkage in transistor size and requirements for improved precision in devices, ion implantation has become an increasingly more delicate and accurate operation. Implantation angle has become extremely important as transistors have decreased in size and voltage specifications. Adjustment and pocket implants, channeling implants, and high accuracy sidewall and HALO implants have become requirements for high performance, with little to no tolerance for incorrect implantation placement.

FIGURE 1. Illustration of wafer slicing angle and associated offset.

Older generations of ion implanters have been designed with only cursory regard to the extreme precision now required for implant placement. Because of this, semiconductor manufacturers must regularly monitor the implantation angle of these tools as part of normal production operations. In this monitoring, multiple potential issues exist that could cause a misinterpretation of the proper implantation angle, resulting in faulty tool calibration or production of out of tolerance product. This article will describe several variables to be considered when defining the angle of implant for a tool, and offer recommended conditions to achieve reliable and repeatable performance on two older implant tool sets.

The standard production test to determine if the angle of implant is accurate involves implanting 5 to 7 wafers tilted around a theoretical channeling angle, annealing the wafers to activate the implant, and charting the sheet resistance vs. implanted angle to find the channel. This procedure is commonly called a V-curve test. The as-measured channeling angle (found by identifying the minimum sheet resistance of the charted curve for the wafers, or the bottom of the “V”) should be equal to the theoretical channeling angle if the tool set-up is accurate. Unfortunately, the number of steps required by this procedure introduces errors that could lead to a false result. The properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique can all significantly affect the outcome.

Experimental
One of the most commonly overlooked variables that can introduce significant error into measurement of the angle of implant is the wafer which is used for the testing. One relevant silicon property of the wafers, the surface orientation angle offset (angle tolerance of the on-axis cut), has a significant effect. All wafers have a base surface orientation angle offset, as required by the process of slicing the wafers from the ingot (FIGURE 1).

This offset can directly translate into an offset in the V-curve measurement, depending on the angular rotation of the slice. It has been shown in previous work[3] that channeling is minimized at implant angles higher than 0.5°. In this work, the effect of the orientation angle offset on channeling was similarly studied. Implants were performed with 200mm, , N-type (phosphorus-doped) CZ wafers of resistivity 3-5 Ω-cm, surface orientation angle of 0.0+/-1°(on-axis ), Oi spec of <=32 ppma (ASTM-79), and LLS of <20 @0.20µm. The wafer type was chosen for use with Boron implant (P-type dopant) and the orientation was picked for its good channeling properties. Using the above specification, wafers were chosen at various extremes of the angle window (close to 0° and close to 1°) in order to characterize the effect of wafer angle variation. Other silicon properties shown in the spec above, such as surface defects, oxygen concentration, and resistivity are in the standard range for a typical test wafer. These parameters have a lesser effect on the implant angle measurement and were not explored in this study.

FIGURE 2(L). Comparison of Varian E500 V-curves generated using Thermawave vs TRS-100. FIGURE 3(R). Effect of wafer orientation angle offset on V-curve of Axcelis Optima MD.

The two implant tool types used were an Axcelis Optima MD implanter and a Varian E500 implanter. Implant conditions were chosen as follows based on experimentation and comparison of common processes among multiple manufacturing facilities utilizing several tool types: Boron11 at 100 keV energy, 1.0e14 ion/sq dose, 35° tilt, and 0° twist. Boron11 was chosen as the dopant for its small mass and channeling properties, as discussed in Downey, et.al.[2] Energy of 100 keV is high enough to prevent outgassing of the dopant during the anneal process, and 1.0e14 ion/sq dose was chosen to place the resultant resistance as measured on a standard Tencor RS-100 into a stable range for the measurement equipment.[1] For all tests, the ion beam was optimally tuned to minimize beam instability or non-linearity. The potential process variables influencing beam steering on the tool were not explored during this experimentation, but it should be commented that an improperly tuned ion beam will also significantly affect the result. A tilt angle of 35° was chosen as the optimal channeling condition. Although multiple potential channeling angles exist for [100] N-type silicon wafers, the angle of 35.26o has shown the most sensitive, clear channel for implant angle testing[1], and it is also recommended by Varian Semiconductor[4]. A twist angle of 0° was applied for best resolution of the channel in all but one of the tests, which utilized a rotation angle of 90° to characterize the effect of the wafer substrate angle offset.

The anneal process needed to be selected in such a way as to eliminate any variation or sensitivity due to temperature of anneal, anneal time, or even annealer tool type. An anneal temperature of 1060oC for 30 seconds was selected from earlier work[1] as the condition at which small temperature variations can be tolerated. Two types of annealer tools were used – an Axcelis Summit furnace annealer, and an AG Associates 8800 lamp annealer – to determine if the V-curve could be shifted through anneal by varying the tool type.

FIGURE 4. Effect of wafer orientation angle offset and wafer rotation on V-curve of Varian E500

Measurement of sheet resistance is well documented for ion implant processing. For this experimentation, Thermawave and Tencor RS-100 measurement tools were researched to identify possible areas of concern in the measurement of V-curve wafers. The advantage to Thermawave processing is the elimination of the need for anneal after implant, removing this source of potential variation. Also, a previous experiment with a different implant has shown that the Tencor RS-100 produces a sharper V-curve than the Thermawave (see sample V-curve in FIGURE 2). Therefore, the Tencor RS-100 tool was chosen for the present work. Testing on the Tencor RS-100 was performed using both 9-point and 49-point radial measurement patterns.

Results and discussion
By far the strongest effect was observed from the silicon wafer orientation angle offset. In particular, at angles above 0.5o, the effect was so pronounced that it shifted the V-curve. See below graph of two sets of wafers processed with identical implant and anneal conditions. The only difference was the orientation angle offset (0.04° vs 0.68°), as shown in FIGURE 3.

In an effort to further characterize the effect of a larger orientation angle offset of the wafers, testing was performed by rotating the wafers 90o during the implant to measure the change in the resultant V-curve. Using wafers with very small surface orientation offset angles (0.04o), the change in the measured V-curve could not be easily seen. However, using wafers with a surface orientation offset angle above 0.5o (0.68o), the change in the measured rotated V-curve became much more visible (FIGURE 4). Repeatability of the tests using high surface orientation angles was also noted to be inconsistent, with significant variance in results from test to test.

FIGURE 5. Effect of anneal tool and temperature on V-Curve of Varian E500.

Based on the results presented above, it is our recommendation that high-angle offset wafers (above 0.5°) should not be used for implant angle qualifications. It is also recommended that the surface orientation angle of the test wafers be scrutinized if the V-curve produced shows abnormal variance from the expected outcome. To reduce variability from other wafer parameters, we also recommend a tight resistivity specification (ex: 3-5 ohm-cm) for the silicon ingot, and advocate the use of wafers not only from the same ingot, but from the same area of the ingot, to ensure similar properties.

Minor effects were observed from other variables studied. An experiment comparing two anneal temperatures confirmed earlier findings1 of 1060C being the optimal temperature to produce a sharper V-curve (FIGURE 5). The type of anneal tool was also a factor. Although the process was matched as closely as possible through matching of the thermal budget, a difference could be seen between the annealer types (Fig. 5, left). Based on the clarity of the V-curve inflection on the lamp annealer, this tool was used as the benchmark for anneals during other experiments.

FIGURE 6. Effect of measurement map resolution on V-Curve of Axcelis Optima MD.

As for the Sheet Resistance measurement, very little to no effect was observed from varying the measurement pattern and number of measured points. A 9-point measurement showed the same accuracy as a 49-point measurement, making the additional points unnecessary (FIGURE 6).

Conclusion
As a result of this testing, multiple recommendations can be made to ensure accurate and repeatable measurement of the implant angle of a tool. These areas can result in significant variation of results if not accounted for during testing. The silicon quality of the wafers is one of the most overlooked variables in performance of implant angle measurement. The surface orientation angle offset can significantly change the measured implant angle, especially in ranges above 0.5° (from on-axis cut). Wafers with angle cut tolerance greater than 0.5° produce inconsistent results, severe enough to shift the sheet resistance values or even the entire V-curve, and are therefore not recommended for implant angle testing.

The parameters used in implantation also contribute significantly to the resolution and accuracy of a V-curve test. Although multiple potential channeling angles exist for [100] N-type silicon wafers, a 35° angle is recommended as the most sensitive, clear channel for implant angle testing.[1,4] The implanted species, energy, and dose all contribute to the stability and repeatability of the measurements. Once implanted, the anneal of the wafer must be tuned to a temperature and thermal budget that minimizes variation, as this will also cause slight changes in results. Finally, measurement techniques can change the outcome of a V-curve test through differences in the measurement tool used.

Once the angle of implant of a given tool is characterized, regular verification (qualification) is highly recommended, especially for events which involve components handling wafer orientation. To save on wafer cost, a test may be performed using 1 or 3 wafers once the baseline sheet resistance of the channeling angle is obtained, and charted through standard SPC techniques. If a failure is observed, escalation of the testing can then include a full 5 or 7 wafer V-curve test to determine if the angle of implant has shifted. Standard troubleshooting for common sheet resistance failure events should be included in disposition of a failure, since hardware issues in the form of leaks, contamination and other failure modes can influence the sheet resistance measurement obtained during angle testing.

Acknowledgments
The authors would like to thank TI silicon material technologist Thomas McKenna for valuable insight into starting material properties, as well as Jeff Bell of SUMCO-USA for providing substrate orientation angle data.

1. Rathmell, M.A. (2006). Implant Angle Monitoring – A Comparison of Channeling Features. Ion Implantation Technology Conference Proceedings, Marseille, France, June 11-16.

2. Downey, D.F., Arevalo, E.A., Eddy, R.J. (2000). The Significance of Controlling “Off-Axis” (from 1-0-0) Oriented Si Wafers During High Angle Implants. Ion Implantation Technology Conference Proceedings, Alpbach, Austria, September 17-22.

3.Guo, B.N., Variam, N., Jeong, U., Mehta, S., Posselt, M., & Lebedev, A. (2002). Experimental and Simulation Studies of the Channeling Phenomena for High Energy Implantation. Ion Implantation Technology Conference Proceedings, Taos, New Mexico, USA, September 22-27.

4.Canning, Stephen, (7/17/2006). BKM – System related Checks for Process Control, PSB2621A, Varian Semiconductor VSEA Product Support Bulletins, Pg. 6.

BOBBY ISAACS is an Ion Implant Fabrication Engineer for Texas Instruments’ DMOS5 manufacturing site in Dallas, TX ([email protected]). ANYA CORNELL is an Ion Implant and Silicon Processing Engineer for Texas Instruments’ MFAB manufacturing site in Portland, Maine.([email protected]).

Leveraging ion implant process characteristics to facilitate 22nm devices

March 1, 2011

Executive OverviewCertain inherent process characteristics such as precision, cleanliness, control and high productivity have been the hallmark of the entire implant industry for some time. Coupled with new capability, implant has become less of a commodity product and more enabling. In fact, the makers of the industry’s next-generation devices are looking to implant to improve established doping applications and facilitate new precision materials modification applications to provide device performance and yield improvements required for 22nm.

James L. Kawski, Varian Semiconductor Equipment Associates, Gloucester, MA USA

Recently, implant has re-emerged as an enabler improving device performance and process variability that would otherwise unacceptably degrade as technology moves to 22nm.

It is becoming more and more apparent that subsequent node transitions will expose new device performance and process limitations driven by scale and physics. Also, tool performance specifications that for several nodes have been taken for granted, will start to become obsolete. In particular, CMOS transistor yield is adversely affected by scaling due to increasing leakage current from multiple sources. The formation of highly activated ultra shallow junctions (USJ) that are both stable and abrupt is a significant challenge [1]. To circumvent this dynamic, the industry has developed damage engineering strategies through cryogenic implant technology and co-implants.

Other limitations are emerging that are impacting other process areas in the fab. Using implant as a precision material modification (PMM) tool, in contrast to its traditional role as a semiconductor dopant tool, provides enabling technology and new applications to drive total available market (TAM) growth. For example, in the formation of ultra-sensitive gate regions, previously acceptable amounts of photoresist line edge roughness (LER) have become a source of threshold voltage variability that will increase leakage current and add to yield loss.

Cryogenic ion implant

A variety of complex device problems present themselves at the threshold of the 22nm technology node, particularly for boron-doped PMOS transistors. Dopant activation and defect creation at the sub-surface source/drain junction and surface regions become significant limiting issues. Through techniques referred to as damage engineering, implant is able to neutralize these effects and enable transition to 22nm.

Boron source/drain doping for PMOS transistors are run on high current ion implanters with beam powers that would normally elevate wafer temperatures that would cause photoresist masks to deform. Historically, simple backside liquid cooling schemes using commercially available chillers would be adequate to keep wafer temperatures from exceeding 70°C.

To facilitate low leakage, high quality sub-surface junctions, high dopant activation and low surface defectivity in the implanted region must be uniformly amorphous.

After milli-second flash or laser annealing, a low-defect, low-resistivity source/drain is desired. With device features at 22nm, junction depths must be under 10nm to minimize short channel effects (SCE). At these junction depths, natural dynamic annealing occurs during the implant process creating interstitial vacancy clusters at room temperature and above. By cooling the wafer during implant it has been demonstrated that self interstitials present at the end-of-range of the implant are reduced. This results in a significant reduction in dopant diffusion and deactivation. It has also been widely reported that lower temperatures down to -100ºC are the most effective [2]. With the expansion of cryogenic cooling into medium current applications such as HALO, maintaining wafer temperature during implant down to -100ºC will be absolutely essential.

Implementation of cryogenic wafer temperatures during implant at high vacuum present a rather significant engineering problem. Varian Semiconductor Equipment Associates (Varian) PTC II hardware has achieved the required temperature range while maintaining ultra-low particle performance and high productivity. Considering the added time necessary to cool and return the wafer to room temperature, Varian’s VIISta platform with batch load lock capability optimized this implementation for maximum productivity.

Molecular dopants

Another proven technique to enhance device performance and yield is through molecular dopants. For years BF2 has been used in the industry with excellent results. Recently the use of carborane (C₂B₁₀H₁₂ – “CBH”) has proven an effective and stable option to introduce carbon into the lattice during PMOS source/drain doping.

CBH provides multiple benefits including reduction of end-of-range (EOR) defects, improving dopant activation and reducing lateral diffusion. A reduction of junction leakage (through diode leakage studies) of 50% has been reported [2]. The deactivation and eventual reactivation of boron in annealed silicon has been shown to benefit greatly from the use of cryogenic implant. Significant improvement in sheet resistivity when CBH is implanted at -100ºC compared to room temperature as illustrated in Fig. 1.

Figure 1. The best R_s/X_j performance has been shown @ -100°C implant temperature. The colder the better for R_s/X_j control.

Varian’s experience with Synopsis’ Technology Computer Aided Design (TCAD) Software has shown that increased surface activation of boron is due to ultra-shallow carbon associated with CBH [3].

Figure 2. Drive current and leakage current of PMOSFET with CBH.

Studies have shown that ultra shallow carborane implantation into pMOS S/D extensions provided enhanced surface activation and reduced sub-surface junction leakage [4]. When comparing the use of a pre-amorphization implant using Ge with and without CBH, the results were striking (Fig. 2). Drive currents of pMOS at -1.1V supply voltage increased by 20% with the use of CBH. Reduction of parasitic resistance and increased activation at the surface was responsible. Also, a demonstrated reduction in leakage current has been shown, which can be attributed to lower junction defectivity.

Tighter angle control

Prior to 32nm half-pitch, post-implant anneals would effectively smear out dopant profile variations resulting from “across wafer” or “across device” angle variations. Beam angle is affected by three prime components: 1) Global steering angle caused by beam tuning repeatability issues, 2) Local steering angle controlled by beam optics design, and 3) Within-device angle spread due to space charge effects [5]. It has been shown that for 32nm devices, as little as 1º of beam steering angle variation during extension implants can lead to a 3% reduction in Idsat [6].

To meet these angle accuracy demands, sophisticated beam angle measurement and adjustment technology has been developed that provides both vertical and horizontal control [7]. Current available technology has proven capability to control beam angle deviation down to 0.1% resulting in marked improvements to NMOS and PMOS I_dsat.

Uniformity

It is generally accepted that uniformity and precision go hand in hand. Ultimately, control of non-uniformity will result from reducing variability in the implanter at various points in the beam-line. The effort to control variability will result in a cumulative set of added controls that ultimately increase an implanter’s flexibility for other applications. So it is with the current state of ion implant. Uniformity can be defined wafer-to-wafer, die-to-die and transistor-to-transistor. Micro-uniformity is of increasing importance as transistors get smaller and die get larger.

Precision dopant placement is affected by both ion beam dynamics and wafer handling capability. Controlling ion beams is particularly challenging since tool makers have to deal with space charge where the main challenge is transporting beams of like charged ions that naturally diverge. After years of development, ribbon beams have become a controllable means of beam transport. This development occurred at the beginning of the decade facilitating the move to single-wafer platforms. Also, wafer handling systems using highly flexible rotational platens that can reposition wafers without removal from the beam path provide exciting new capability with no loss in throughput. For example, implant can compensate for variability in other processes such as photolithography, chemical mechanical planarization, and spike anneal. Scanning an implant at different rotation angles creates a cross-wafer doping distribution that is intentionally non-uniform in opposition to the incoming non-uniformity from other process steps. This has been successfully implemented, particularly for improving threshold voltage variability on CMOS transistors, on medium current tools.

For the future, it is expected that enhanced uniformity control and beam angle control will contribute to new device integration efforts. As an example, device makers are looking to these technologies for development of 3D structures.

Energy contamination-free implant

Sub-2 keV implants are necessary to obtain the required ultrashallow junction (USJ) to control SCE for sub-45nm devices. These low energy beams lose more beam current due to space charge effects adversely affecting productivity. Instead of “drifting” these low energy beams, implanter makers have resorted to accelerating the beam, then decelerating it just before the wafer to maintain beam current and increase productivity. This deceleration creates neutralized ions that do not fully decelerate thereby entering the wafer at a higher energy. This energy contamination creates a tail on the profile that will increase leakage at the sub-surface junction. Recent improvements to high current beam lines have enabled full energy purity capability for deceleration technology applied to recipes from 500eV to 2keV.

Figure 3. Low-energy boron SIMS plot: The latest generation of high current implanters provide full energy purity at maximum throughput.

Since dopant activation is critical, device makers can now utilize phosphorous for NMOS source drain implants. Phosphorous has a higher activation level over arsenic. Historically, heavier arsenic was the dopant of choice because implanters ran more productively at higher energies and it diffused less during activation. Now device makers can run phosphorous at or below 2keV, achieving high activation while maintaining high productivity. Adding carbon co-implants to the NMOS source/drain region retards phosphorus diffusion during activation and keeps the junctions shallow. With this new implant technology, device makers can now achieve very high productivity free of energy contamination.

Improving lithography through materials modification

Implanting dopant atoms changes the conductivity of silicon. The use of implant with other materials results in physical or chemical changes to the target. Utilizing PMM with lithographic applications has resulted in several growth opportunities for implant. Reduction of line edge roughness (LER) or line width roughness (LWR) is one widely investigated application.

Figure 4. Comparison of implanted photoresist samples to a reference sample showing CD and LWR changes.

LER does not decrease as line-widths do. Consequently, it becomes a larger percentage of overall variability. Short wavelength LER and LWR is due to residual resist molecules left after development while long wavelength LER is due to interference patterns created by patterning light sources. LER for lithography typically uses heavy ions such as argon, neon or silicon which result in sputtering processes at the wafer when applied. Reduction or elimination of resist roughness through implant is enhanced by exploiting the angular dependence of sputter rates. In one study, silicon and argon were evaluated by implanting at a fixed dose of 5E15 ions/cm2 with a fixed tilt angle of 60 degrees [8]. In this analysis, both critical dimension and LWR were measured (Fig. 4). The ion implanted resist shows a change in CD as well as a reduction in LWR. At the same energy, argon still exhibits a greater CD loss and LWR reduction. As has been shown, non-reactive ion beam species has won out in comparative studies with other techniques providing anywhere from a 25% to 500% improvement [9].

Conclusion

Through a combination of established implant technology and newly developed hardware, ion implant is providing enabling applications for 22nm device integration. Cryogenic ion implant, where the wafer is held at temperatures down to -100C during implant, has proven to reduce device leakage and increase dopant activation. When used in conjunction with molecular dopants, such as carborane, where carbon can be introduced into PMOS source/drains, as much as a 50% reduction in junction leakage has been reported. Improvements in beam angle control have proven to increase device speed directly through improvements in Idsat. Tradeoffs between high productivity and low energy contamination have been prominent in the past. New hardware designs have attained the elusive goal of full energy purity and high productivity for the lowest energy implants. Finally, the use of implant for precision material modification has shown significant promise to extend other process capabilities namely in lithography through reduction of line edge roughness.

Acknowledgments

The author would like to thank Chris Campbell, Benjamin Colombeau, Fareen Khaja, Niranjan Khasgivale, Patrick Martin, Curt Norris, Tom Parrill and Dennis Rodier for their support.

References

F. Khaja, B. Colombeau, T. Thanigaivelan, D. Ramappa, T. Henry, “Benefits of Damage Engineering for PMOS Junction Stability,” 2010 Inter. Conf. on Ion Implant Technology, Kyoto, Japan, to be published.
C.I. Li, P. Kuo, H.H. Lai, K. Ma, R. Liu, H.H. Wu, et al., “Enabling Solutions for 28nm CMOS Advanced Junction Formation,” 2010 Inter. Conf. on Ion Implant Technology, Kyoto, Japan, to be published.
C.I. Li, T.M. Shen, H.H. Lai, P. Kuo, R. Liu, H.Y. Wang, et al., ” Integration Benefits of Carborane Molecular Implant for State-of-the-Art 28nm Logic PFET Device Manufacturing,” IEEE Electronic Device Letters, to be published.
B. Colombeau, T. Thanigaivelan, E. Arevalo, T. Toh, R. Miura, H. Ito, “Ultra-Shallow Carborane Molecular Implant for 22nm Node p-MOSFET Performance Boost,” Inter. Workshop on Junction Tech., 2009, pp. 27-30.
A. Renau, “Device Performance and Yield – A New Focus for Ion Implantation,” Inter. Workshop on Junction Tech, 2010, pp 1-6.
H.J. Gossman, T. Romig, et al., “Precision Requirements for Advanced HP Logic Implantation,” Solid State Technology, July 2007.
J.C. Olsen, et al., 17th Int. Conf on Ion Implantation Tech, Monterey, USA, pp. 129-132, 2008.
P. Martin, L. Godet, A. Cheung, G. de Cock, C. Hatem, “Ion Implant Enabled 2X Lithography,” 2010 International Conf. on Ion Implant Technology, Kyoto, Japan, to be published.
C.R.M. Struck, R. Raju, M.J. Neumann, D.N. Ruzic, “Reducing LER Using a Grazing Incidence Ion Beam,” Proc. of SPIE Advanced Lithography 2009 Vol. 7273-49.

Biography

James L. Kawski received his BS in electrical engineering from The Rochester Institute of Technology and is manager of market research and communications at Varian Semiconductor Equipment Associates, 35 Dory Road, Gloucester Massachusetts, 01930; ph.: 978-282-2000; email [email protected].

Solid State Technology | Volume 54 | Issue 3 | March 2011

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