Category Archives: Materials


A novel SACVD PMD invention sets the benchmark for helium reduction efforts by achieving four key objectives: cost reduction, quality, process robustness and productivity.

BY JAE HEE KIM, Thin Film Dielectric Fabrication Engineering, Texas Instruments, Dallas, TX

The United States is the world’s largest helium supplier and half of its supply comes from a helium reserve regulated by the Bureau of Land Management just outside of Amarillo, Texas. As many predict, at the current rate of production the maximum expected life of this reserve is 2020. As a result of a shortage that began in 2013, the cost of bulk helium has been increasing significantly (FIGURE 1).

Helium 1

Considering semiconductor manufacturing is one of largest helium consuming industries [2], it becomes crucial to invest continuous efforts to minimize helium usage during wafer fabrication processes and to identify new opportunities for helium reduction. In this article, we’ll take a look at a new innovative process to do just that.

Sub-Atmospheric Chemical Vapor Deposition (SACVD) for pre-metal layer consumes a significant amount of helium to assist in process gas delivery during deposition and in-situ chamber clean which makes the best candidate for helium reduction effort benchmarking. Also, SACVD Pre-Metal Dielectric (PMD) consists of various processes including phosphosilicate glass (PSG) and borophospho-silicate glass (BPSG) which makes the fan-out process more applicable for a bigger impact on helium reduction. So how do we do it?


There are four key objectives to a new SACVD PMD process development that my team has looked at: cost, quality, process robustness, and productivity. First, a new carrier gas was identified to maximize helium usage reduction. Second, solutions to both new hardware and process conditions were developed for quality improvement. A new blocker plate was qualified to improve within wafer thickness uniformity. Additionally, gas conditions were developed to improve the gap-fill capability for leakage reduction. Third, a new pressure condition was qualified for process robustness improvement. An old two-step baseline process was designed for better gap fill by depos- iting initial 4kA film at 700Torr for lower deposition rate and the rest of the film at BKM pressure, 200Torr for better cycle time. However, this baseline two-step process, which operates at near atmospheric pressure on a sub-atmospheric CVD tool platform, is marginal for pumping speed degradation which leads to inline defect. Susceptibility of defect formation was reduced by lowering process pressure from 700Torr to 600Torr during the initial PMD layer. Last, overall process conditions were evaluated to achieve a desirable deposition rate in order to ensure comparable manufacturing throughput. Furthermore, a new process condition was selected to avoid process chamber restriction for flexibility of manufacturing.

New process carrier gas identification

Initial process development was divided into two categories: BPSG and PSG. Development began with PSG since there is one less process parameter, Boron compared to BPSG process. Preliminary tests showed that a 100 percent N2 carrier drives an unstable film thickness range. Based on findings, a helium and nitrogen mix carrier gas was selected for further process evaluation. The main focus at this stage of evaluation were to identify process conditions including a helium and nitrogen mix carrier gas flow to achieve maximum helium savings, comparable cycle time, and thickness uniformity improvement.

Process condition development

Based on design of experiments (DOE) with four key process parameters (N2, He, O3, spacing), we learned that deposition rate is faster with increasing He and slower with increasing N2 and O3. Thickness uniformity degrades with total carrier gas flow. Based on DOE results, initial proposed condition was carrier 5500sccm (3:1 = N2:He), O3 3000sccm, spacing 200mils for better thickness uniformity and shorter cycle time while saving the maximum amount of helium.

Unfortunately, this condition degraded at baseline margin to form voids in 700Torr deposition film due to faster deposition rate. Focus was then shifted to identify a recipe condition that lowers the deposition rate during 700Torr deposition for a better gap fill capability which also can be used for both 200Torr PSG and two-step PSG to ensure manufacturing flexibility.

Based on deposition rate DOE with three parameters including Ozone, tetraethyl orthosilicate (TEOS) and spacing (TABLE 1), ozone flow has first-order effects on the deposition rate, and spacing has second-order effects. TEOS flow has third-order effects on deposition rates but also reduces dopant concentration of film. Temperature change was not considered since it affects other recipe conditions at a greater degree. Increasing pressure was also not considered since the process already operates at a high pressure of 700Torr.

Helium Table 1

Then it was decided to include Ozone and spacing, in addition to helium and nitrogen, into further process characterization. We ran comprehensive three factorial DOE to deposit 4kA PSG film at 700Torr at various settings of total carrier flow, spacing, and ozone. This was in order to achieve a lower deposition rate for better gap fill and good thickness uniformity. DOE conditions were determined based on JMP prediction profiler and calculators to evaluate a wide spectrum of different deposition rates at 700Torr and thickness range.

To evaluate the DOE result, two techniques were used. First, wafer samples were prepared by sputtering top down until they reached the very initial layer of PMD to open up any voids that are present in PSG film. Effectiveness of gap-fill capability was rated by quantifying a number of voids on the scanning electron microscopy (SEM) images captured at same magnification on the consistent location of the wafer sample. This is a more effective technique than collecting transmission electron microscopy (TEM) on a defined location on samples since top down SEM can capture broader areas of wafer samples. Second, wafers were also submitted for dynamic secondary ion mass spectrometry (SIMS) to ensure if the dopant profile throughout PSG film is comparable to the baseline. This critical step is to verify that there is no sign of unstable dopant distribution that could lead to any adverse effects, such as increased etch selectivity or poor gettering (FIGURE 2).

Helium 2

Based on DSIMS collected, it was found that the dopant concentration profile becomes unstable if the total carrier gas flow is less than 5500sccm. Phosphorous (P) concentration profile shows fluctuation all throughout the film at a total carrier gas flow less than 5500sccm while phosphorous percent profile was steady at total carrier gas at 5500sccm or higher (FIGURE 3).

Helium 3

Among many conditions that satisfy a total carrier gas flow of less than 5500sccm, when ozone flow is 5000sccm and total carrier gas is 5500sccm with a 3:1 ratio of nitrogen to helium, the top down SEM result shows a greatly reduced number of voids in film. This means the deposition rate during 700Torr is slow enough to improve gap-fill capability. At the same time, Ozone flow at 5000sccm was fast enough during 200Torr to maintain a comparable cycle time. Therefore, this condition can be used for both single step PSG and two-step PSG which allows flexibility for manufacturing to run both processes without equipment restriction. Dynamic SIMS also verified that this condition provided a stable dopant profile. Thickness uniformity was also comparable to the baseline on this recipe condition. Therefore, spacing 200mils, ozone 5000sccm, and a total carrier flow 5500sccm was chosen as a finalized new PSG condition.

For the BPSG process, the same technique was used for evaluation. DSIMS was used to ensure both Boron and phosphorous concentration profiles are comparable. The same carrier gas conditions with nitrogen and helium at a ratio of 3:1 of 5500sccm and Ozone 5000sccm were selected for the final condition. TEOS was increased from 600mgm to 800mgm to make sure the deposition rate is comparable to maintain manufacturing cycle time at PMD (TABLE 2).

Helium Table 2

Flash parametric legacy issue improvement

A high aspect ratio of device structure can cause voids in PMD that lead to poor isolation and yield loss. There are many contributing factors that modulate PMD voids, including a stacked gate vertical profile and a sidewall spacer profile. Among all contributing factors, however, a void-free PMD process was proven to be the most effective way to minimize leakage. The void-free PMD was achieved by qualifying a new two-step PSG process with a mix carrier gas.

The new two-step PSG process with a mix carrier greatly lowers the deposition rate during the initial PMD layer. This helps deposit film more uniformly at higher pressures to minimize voids, while depositing the rest of the PMD at a faster deposition rate at lower pressure helps to compensate cycle time loss from the initial deposition.

The new two-step PSG alleviates leakage susceptibility on the wafer edge and reduces sensitivity to the PMD void-contributing factors by adding significant margins to leakage failure due to voids. Notably, the PMD gap-fill improvement added significant integration marginality between the sidewall spacer profile and the PMD which led to lower process and tool sensitivity at the sidewall spacer etch. This increases manufacturing capacity by releasing sidewall spacer etch process chambers with historical leakage failure susceptibility to production. Most importantly, parametric outlier probability was greatly improved by 20 percent and a zero standard parametric failure rate was achieved by qualifying void-free PMD (FIGURE 4).

FIGURE 4. Void-free PMD (right) shows excellent gap fill while baseline PMD (left) shows a void filled with W [3].

FIGURE 4. Void-free PMD (right) shows excellent gap fill while baseline PMD (left) shows a void filled with W [3].

Process robustness improvement

There were technical challenges with center cluster defects on the new two-step process. Center cluster defects affected isolation contact resistance. Based on TEM (FIGURE 5), defects formed around where a low deposition rate completed and a faster deposition rate resumed. Dynamic SIMS showed a phosphorous concen- tration peak at the defect which explained why this defect had a high contact etch selectivity.

Helium 5

After exposing the test wafer for 24 hours at atmosphere, haze was formed on its substrate. Time of flight secondary ion mass spectroscopy showed that haze was caused by a reaction between excessive phosphorous and atmospheric moisture. Additionally, a repeatability test showed that the tail of cluster defects extended towards gas exhaust. Based on these findings, this baseline two-step process which operates at near-atmospheric pressure on a sub-atmospheric CVD tool platform is marginal to maintain sufficient pumping speed during pressure transition from high process pressure to low process pressure (FIGURE 6). This significantly increased the chances of forming center cluster defects with a heavier carrier gas. This is because the pumping speed is lower at a higher pressure and mean residence time is longer at a higher pressure. Additionally, conductance is lower with N2 than with He due to heavier molecular weight.

Helium 6

In order to address this issue, the new two-step process was reevaluated and a new process condition was developed. As summarized in TABLE 3, it was decided to maintain the same carrier gas flow to maintain bulk helium savings. Pressure condition for the first deposition step was modified from 700Torr to 600Torr. This new two-step process improved robustness by reducing risks of pumping speed degra- dation during the pressure transition from 600Torr to 200Torr. The new two-step process is also able to deliver a strong PMD void-fill improvement by maintaining a zero parametric failure rate for leakage.

Helium Table 3

Thickness uniformity improvement

The new SACVD PMD invention took part not only in process development but also in hardware improvement. The new process with a baseline helium blocker plate that helps uniform process gases dispersion showed higher within wafer thickness range which appeared on wafer substrate as in forms of lightly discolored spots. Based on Energy Disperse Spectroscopy (EDS) and Dynamic SIMS, defects were a part of the top 270A of PSG film. The location of spots were nicely matched to the hole pattern of the helium blocker plate. The nitrogen blocker plate was qualified as it consisted of the same material as the helium blocker plate but had a more dense hole pattern. It was not only able to eradicate the anomaly on the surface film but also to alleviate the baseline starburst pattern on the deposited film.

DSIMS confirmed that the dopant profiles on the nitrogen blocker plates are comparable to the ones on the helium blocker plate. The nitrogen blocker plate improved within wafer thickness uniformity by 35 percent on a new PSG film ranging from 12kA to 16kA compared to an old PMD baseline performance (FIGURE 7). Consequently, this improved the process capability index at post PMD Chemical Mechanical Polish (CMP) by improving process targeting based on improved thickness uniformity.

Helium 7

Manufacturing and engineering productivity increased, as well, due to reduced tool down time. New blocker plate qualification also alleviated the sensitivity of film thickness uniformity to the heater age and possibly helped to extend heater life on the PSG chambers and reduce tool down time for range failure.


This novel SACVD PMD invention successfully set the benchmark for helium reduction efforts by achieving four key objectives: cost reduction, quality, process robustness, and productivity. It brings a substantial impact on bulk helium gas savings with worldwide limited supplies and increasing demand. The new PMD reduces bulk helium usage by 80.4 percent and 77.1 percent for PSG and BPSG respectively during deposition and completely eliminates helium usage during in-situ chamber clean.

This new process achieved outstanding gap-fill capability by lowering the deposition rate at initial PMD layer. The process successfully eliminated leakage failure at parametric by adding significant process integration marginality for void formation. It also improves process robustness by reducing risks of pumping speed degra- dation during the pressure transition from 600Torr to 200Torr. Process conditions are carefully developed for comparable manufacturing throughput and harmonized between single step PSG and two-step PSG in order to ensure manufacturing flexibility. Lastly, new hardware qualification also helps improve quality and productivity by lowering within wafer thickness range.


[1] C. Kaneshige, 2013, an excerpt from GE Healthcare published in 2012
[2] Semiconductor Industry Association, August 1, 2012, Hearing on “Helium: Supply Shortages Impacting our Economy, National Defense and Manufacturing” (Hearing held on July 10, 2012). Testimony for the Record of the Semiconductor Industry Association.
[3] D. Rodriguez, 2014, unpublished

AKHAN Semiconductor, Inc. (AKHAN SEMI), a developer of diamond semiconductor technology, this week announced that it is deploying 200mm manufacturing equipment and process in its new production facility in Gurnee, Illinois, continuing its preparation for delivering AKHAN diamond semiconductor based-technology products to the company’s first commercial customer this quarter.

“The proven, high-yielding 200mm semiconductor manufacturing process is proving ideal for the production of a wide range of semiconductors – sensors, MEMS, analog, power management – that are embedded in the rapidly growing number of connected devices, from smartphones and tablets to cars, home appliances, wearables, and commercial and industrial applications,” said AKHAN COO Carl Shurboff.

According to market research firm Gartner, Inc., the number of Internet-connected devices, now referred to as the Internet of Things, will grow from 6.3 billion in 2016 to more than 20 billion in 2020.

This explosion in connected products is driving high global demand for all types of new semiconductors to power this new era of connected computing. SEMI noted in its Global 200mm Fab Outlook to 2018 that 200mm fab capacity is expected to grow from 5.2 million wafer starts per month in 2015 to more than 5.4 million in 2018.

“The timing for our diamond-based semiconductor technology’s market debut could not be better,” said AKHAN CEO Adam Khan. “By using man-made diamonds at the core of our new chip technology, we are ushering in a new generation of semiconductor solutions that operate at higher temperatures, are thinner and require less power. These are exactly the attributes required for all the products that make up the Internet of Things.”

The AKHAN diamond semiconductor based technology will enable a new generation of commercial, industrial and consumer products such as flexible and transparent displays that can be used in wearables and thinner consumer devices that last longer. On the commercial side, AKHAN is already developing new diamond windows for industrial, defense and aerospace applications.

AKHAN’s technology is based on a new process that uses man-made diamond rather than silicon to produce new chip materials. It is a result of the marriage of two scientific breakthroughs: the ability to use nanocrystalline diamond (NCD) films and a new doping process the makes it possible to use NCD as a semiconductor material.

The new AKHAN production facility was opened in mid-November. The company is actively hiring to staff the new facility which is expected to employee 100 people in the next two years.

The Critical Materials Council for Semiconductor Fabricators, originally established by ISMI/SEMATECH in the early 1990’s, will be managed by TECHCET CA LLC starting January 01, 2016. Under its new name CMC Fabs, the membership-based organization of semiconductor fab & fabless manufacturers will continue working to identify and remediate issues impacting the supply, availability, and accessibility of both current and emerging semiconductor process materials. In keeping with SEMATECH tradition, the work of the international council takes place in a non-competitive environment for the benefit of the semi device fabrication community. Topics addressed are identified and prioritized by the member companies.

The organization has a new website at, which includes an overview of the Council’s mission, news of upcoming events and a Members Only portal for access to minutes of monthly phone/WebEx meetings and workshop details. The site also features access for Members to the TECHCET Critical Materials Reports and the related quarterly updates.

The next face-to-face meeting of CMC Fabs will take place May 3-6, 2016 in Hillsboro, Oregon. The meeting will include the annual CMC Materials Seminar held on May 5-6 that is open to the public. Sessions include a market briefing, supply chain issues and methods, the evolution of emerging materials in ALD / ALE, and the materials revolution around carbon. Speakers will be drawn from fabs, suppliers and analysts to address topics of concern and interest to the Council, and the semiconductor materials supply chain.

CMC Fabs is a unit of TECHCET CA LLC, a firm focused on Process Materials Supply Chains, Electronic Materials Technology, Materials Market Research and Consulting for the Semiconductor, Display, Solar/PV, and LED Industries. The company has been responsible for producing the SEMATECH Critical Material Reports since 2000.

Packaging Materials

December 11, 2015

According to a newly released report from SEMI and TechSearch International, the $18 billion semiconductor packaging materials market will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC leadframes, underfill, and copper wire. Segments such as wafer-level packaging (WLP) dielectrics will experience stronger unit volume growth over the same timeframe. Packaging materials include laminate substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and thermal interface materials.

Packaging materials are a key enabler to increasing the functionality of thinner, smaller packages consumed in smart phones and other mobile products. Many options are currently available to meet form factor requirements for mobile products such as stacked-die chip scale package (CSP), land grid array (LGA) and fine pitch ball grid array (FBGA) packages, package-on-package (PoP), wafer-level package (WLP), Quad Flat No-lead (QFN) and other packages, using both wirebond and flip chip interconnects.

Key trends include:

  • FO-WLP is emerging as a disruptive technology, changing the demand for the types of packaging materials used in the industry
  • Need for WLP dielectric materials for multi-layer redistribution layers
  • New materials for laminate substrates and underfill to pitch decreasing pitch and bump height trends in flip chip packaging
  • Improved mold compounds for warpage control and package reliability
  • For QFN packaging, cost optimization through enhanced designs and reduced plating area; higher lead counts (routable); improved power dissipation
  • Continued growth in copper and silver wire
  • Materials and processes compatible with tighter tolerances for higher density leadframes and substrate packaging, and for compact multi-die system-in-package (SiP) configurations

Constrained industry growth and the trend towards lower-cost electronics have reshaped the packaging material supplier landscape. Changes in material sets, the emergence of new package types, and cost reduction pressures have resulted in recent consolidation in various material segments. In addition, materials consumption in some segments is declining given the changes in package form factors and the trend towards smaller, thinner packaging.


December 11, 2015

Beyond the wafers themselves, the semiconductor industry employs thousands of different kinds of materials. These range from the materials used in wafer manufacturing — chemicals and gases, photoresists and developers, anti-reflection coatings, CMP slurries, adhesion promoters, etc. — to the materials used in the manufacturing equipment and the wafer carriers. On the packaging side, materials include laminate substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and thermal interface materials.

The market for semiconductor materials is on the same level as capital equipment. In 2015, SEMI reported that the total wafer fabrication materials and packaging materials markets in 2014 were $24.0 billion and $20.4 billion, respectively. Comparable revenues for these segments in 2013 were $22.7 billion for wafer fabrication materials and $20.4 billion for packaging materials. The wafer fabrication materials segment increased 6 percent year-over-year, while the packaging materials segment remained flat. However, if bonding wire were excluded from the packaging materials segment, the segment increased more than 4 percent last year. The continuing transition to copper-based bonding wire from gold is negatively impacting overall packaging materials revenues.

For the fifth consecutive year, Taiwan was the largest consumer of semiconductor materials due to its large foundry and advanced packaging base, totaling $9.8 billion. Japan claimed the second spot during the same time. Annual revenue growth was the strongest in the Taiwan market. The materials market in North America had the second largest increase at 5 percent, followed by China, South Korea and Europe. The materials markets in Japan and Rest of World were flat relative to 2013 levels. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets.)