Rudolph Technologies, Inc., has received an order for over $15 million from an unnamed foundry in Asia for multiple NSX 330 Systems.
The systems will be used for inspection of next-generation fan-out wafer level packaging products, including whole-wafer inspection and post-saw inspection. The systems will begin shipping in the fourth quarter of 2015 with the majority shipping in the first quarter of 2016.
“We are pleased to partner with this industry leader to provide the market-leading NSX System for their next-generation packaging line,” said Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit. “Key factors of this win were the systems’ superior inspection sensitivity, capture rate, and throughput for two-dimensional (2D) inspection, while meeting the automation challenges inherent with fan-out wafers and film frames. Additionally, all systems will be equipped with Rudolph’s Discover Yield Management Software that enhances the user’s process analysis capability in real-time, enabling fast yield improvement and increasing the productivity of each tool and the overall fab yield. This level of process visibility is quickly becoming essential to factory efficiency.”
“Rudolph has been enabling its customers’ development of advanced packaging processes for nearly two decades. We are pleased that our experience, combined with our unique fusion of hardware and software solutions, was selected to help our customer quickly ramp and control such a critical project,” said Mike Plisinski, CEO of Rudolph. “The development of advanced packaging solutions is a priority for many of our customers, as more of their customers specify packages utilizing fan-out, panel, and copper pillar technology to reduce the cost of devices while improving performance.”
Plisinski adds, “While the 2016 forecast for the overall semiconductor industry remains relatively subdued at 1.9 percent growth, according to Gartner, the development of next-generation advanced packaging processes continues to be an important growth driver for Rudolph. We are pleased that our comprehensive solutions-process, process control, and software-are helping to enable this growth.”
Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging.
It was originally introduced by Infineon in the fall of 2007. Called eWLB, or embedded wafer-level ball grid array technology, it enables all operations to be performed highly parallel at wafer level. In August of 2008, STMicroelectronics, STATS ChipPAC, and Infineon signed an agreement to jointly develop the next-generation eWLB, based on Infineon’s first-generation technology.
Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.
STATS ChipPAC’s eWLB high volume manufacturing process, for example, today includes automated wafer reconstitution (including wafer-level molding), redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 200mm and 300mm diameters can be supported.
According to a recent report from Yole Développement, the fan-out WLP (FOWLP) market will reach almost $200M in 2015, with 30% CAGR in the coming years. Yole analysts say FOWLP started volume commercialization in 2009/2010 and started promisingly, with an initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. In 2012 big fabless wireless/mobile players started slowly volume production after qualifying the technology.
Every electronic device — whether it is an integrated circuit, an LED, a MEMS device, a passive component or anything else — must be connected to the outside world at some point and this requires a series of process steps to connect the “wiring” and protect the device, typically in some kind of encapsulant.
Wafers of consisting of hundreds or thousands of Individual components are cut up through a process known as dicing or “singulation,” typically by attaching the wafer to a plastic wafer carrier and cutting them with a high speed saw. Many different types of packaging technologies exist, but individual die are typically placed on a leadframe or flip chip substrate; the die attachment process is known as die bonding. This involves a machine known as a die bonder and an electrically conductive die adhesive
The next step is wire bonding, where a gold or copper wire is bonded to the contact pads on the wafer and an I/O pin on the leadrame (or, in the case of flip chip bonding, a ball bond connects the bonding pad on the chip to the substrate, and an underfill adhesive is “jetted’ in to fill voids).
After the chip is electrically connected to the carrier, it is encapsulated in the familiar black epoxy, or an alternative method of protecting the device.