Category Archives: Resource Guide

Gases


December 11, 2015

A variety of gases are used in semiconductor manufacturing for process reactions in chemical vapor deposition, etching, ion implantation and many other processes. They are also used for such diverse purposes as chamber cleaning and purging. Generally speaking, gases are classified as processes gases for the first set of applications and bulk gases for the second. Bulk gases are hydrogen, helium and nitrogen, for example, which can be produced on-site through air separation plants. Process gases are typically supplied in the familiar gas tanks, or sometimes gas tanker trailers if the volume required is high enough. In some parts of the world, underground piping is used to supply multiple fabs

Aside for the gas type, the most common concern is the purity of the gas. Purity is often discussed in the “number of nines” level of purity. Gases that are 99.999% pure, for example, are “five nines” purity, gases that are 99.9999% pure are “six nines” purity and so on. Alternatively, trance contaminants are measured in parts per million (ppm), parts per billion (ppb) or even parts per trillion (ppt). Higher levels of purity are, of course, more difficult to produce and are therefore more costly. They are also more difficult to measure accurately. An ongoing challenge in the semiconductor industry is that gas users — IC manufacturers — tend to specify the highest level of purity available, but it’s often unknown if that higher level of purity actually provides any kind of benefit to device performance or yield. Indeed, sometimes trace impurities have proved to have some kind of beneficial effect and removing them can actually decrease performance.

Another important aspect — some would say the most important aspect — is safety. Gases can be toxic, carcinogenic, flammable, pyrophoric, corrosive and generally hazardous. A silane leak, for example, could result in a pocket of silane in a corner of the fab, which could explode. Arsine and phosphine, commonly used in ion implantation, are deadly in ppb and ppt, respectively. Fortunately, the semiconductor industry has an excellent safety record and danger to fab personnel is minimal — as long as established safety protocols are closely followed. This include storing gas cylinders in well monitored gas cabinets.

Chemical Vapor Deposition


December 11, 2015

Chemical vapor deposition (CVD) is used to produce high-purity thin films. In a typical CVD process, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Frequently, volatile byproducts are also produced, which are removed by gas flow through the reaction chamber.

Microfabrication processes widely use CVD to deposit materials in various forms, including: monocrystalline, polycrystalline, amorphous, and epitaxial. These materials include: silicon, carbon fiber, filaments, carbon nanotubes, SiO2, silicon-germanium, tungsten, silicon carbide, silicon nitride, silicon oxynitride, titanium nitride, and various high-k dielectrics. The CVD process is also used to produce synthetic diamonds.

Applications include shallow-trench isolation, pre-metal dielectric, inter-metal dielectric, and passivation. CVD processes are also important in strain engineering that uses compressive or tensile stress films to enhance transistor performance through improved conductivity.

Additional Reading

Taking 2D materials from lab to fab, and to technology

New materials require new approaches

Deposition equipment market witnesses a year of significant change

Wafer Inspection


December 11, 2015

Wafers need to be inspected at many stages throughout the manufacturing process. Particles and defects need to be detected and classified. Features need to be measured in both the x, y and z direction (critical dimensions and film thickness, for example). Film stoichiometry needs to be measured. Wafer warpage and bow must be evaluated and compensated for. Film stress (either tensile or compressive) is another important measurand as is dopant concentration, adhesion, and dozens if not hundred of other parameters. Variations across the wafer, within each die and die-to-die are also important.

Wafer inspection — also called metrology — is mostly used for process control, to make sure processes are not drifting out of control, As such, measurements are made after each process step — or more infrequently if at all possible since there is a cost associated with every inspection step in terms of capital equipment required, reduced throughput and added particles from increased handling.

Of course, more advanced characterization techniques are also needed for process development and failure analysis.

New inspection challenges include the need to measure more complex device structures such as those found in FinFETs and 3D NAND. The industry is also pushing a wide array of new materials into production, which brings a new set of challenges since each type of material has unique properties when it comes to reflection, refraction, adhesion, stress, etc.

The push to smaller dimensions and thinner films means smaller defects and variations become more important, which often pushes the accuracy, resolution and repeatability limits of today’s measurement tools.

The most common type of wafer inspection tool is the optical microscope. Although still used today for macro inspection, the very small dimension on today’s wafers can only be measured by more advanced means, most notably the scanning electron microscope and the transmission electron microscope. Other commonly used tools include ellipsometers to measure film thickness.

For failure analysis, even more sophisticated surface analysis tools are required, including  ESCA, Auger, EDAX, and Rutherford Backscattering (RBS), among many others.

Atomic Layer Deposition


December 11, 2015

There are four main segments in the thin-layer deposition equipment market – atomic layer deposition (ALD), chemical vapor deposition (CVD), epitaxy, and physical vapor deposition (PVD), also known as sputtering. Although CVD equipment represents the largest equipment type, ALD represents the fastest growing equipment category.

ALD is a technique capable of depositing a variety of thin film materials from the vapor phase. As device requirements push toward smaller and more spatially demanding structures, ALD has demonstrated potential advantages over alternative deposition methods, such CVD and PVD due to its conformality and control over materials thickness and composition. These desirable characteristics originate from the cyclic, self-saturating nature of ALD processes [1].

‪Layers are formed during reaction cycles by alternately pulsing precursors and reactants and purging with inert gas in between each pulse. Each atomic layer formed by this sequential process is a result of saturated surface-controlled reactions. For example, a metal precursor pulse of trimethylaluminum (Al(CH3)3) followed by an oxygen reactant pulse (H2O vapor) results in the formation of a layer of aluminum oxide, a metal oxide compound that can be used as a high-k dielectric.

Building devices atom by atom enables very precise control over the process. Because the ALD process is self-limiting, it results in films with a precise thickness and conformality, even over varied surface topographies. It can be applied to produce different oxides, nitrides or other compounds. ALD provides excellent surface control and can produce thin, uniform and pinhole-free films over large areas by single or tailored multiple layer deposition. Nanolaminates or stacked layers of different materials can also be produced, in a straightforward manner, in the ALD reactor. ​

According to new report by Global Industry Analysts, Inc., the global market for thin layer deposition equipment in semiconductor applications is projected to reach US$13.6 billion by 2020, driven by expanding electronics industry and parallel growth in demand for semiconductor solutions.

In terms of R&D, metal ALD has been challenging because of lack of suitable chemistry and nucleation problems. The development of processes for platinum group metals was a success but need for good industrial processes for many other metals still exists. Metal sulfides are old ALD materials and in industrial use in electroluminescent display production but ALD of selenides and tellurides has been much less studied. The need of chalcogenides in phase change materials and development of alkyl silyl precursors for selenium and tellurium has improved the situation. There is still a need to develop new ALD processes for microelectronics, low-k materials, 2D materials and oxides for transparent TFTs, according to Markku Leskelä, University of Helsinki, Finland.

In addition to applications in microelectronics there are many emerging areas where ALD has been introduced. One important area is energy technology materials. ALD films are used in silicon solar cells as passivation layers and they are extensively studied in many other areas such as dye sensitized solar cells, lithium ion batteries, supercapacitors and fuel cells. Indicative for these and many other applications is the use of known – mostly oxide –processes for protection. Li ion batteries make an exception and new materials and processes have been developed for lithium compounds. Research is also underway to adapt ALD processes to high-throughput roll-to-roll production for printed/flexible electronics.

Key players in the ALD deposition arena include Applied Materials Inc., ASM International N.V., Jusung Engineering Co. Ltd., Lam Research Corporation, Oxford Instruments, Picosun, Tokyo Electron Limited, ULVAC Technologies Inc., Ultratech/Cambridge Nanotech and Veeco Instruments Inc., among others.

The American Vacuum Society hosts an annual conference on Atomic Layer Deposition dedicated to the science and technology of atomic layer controlled deposition of thin films.

References

  1. http://www.sciencedirect.com/science/article/pii/S1369702114001436

Suggested additional reading

Atomic layer deposition goes mainstream in 22nm logic technologies

Successful industrialization of high-density 3D integrated silicon capacitors for ultra-miniaturized electronic components

Particle Atomic Layer Deposition

JVST A – Most Read Atomic Layer Deposition Articles Published in 2014

Chemical mechanical planarization (CMP) is a critical process technology step in the semiconductor wafer fabrication process. In this process step, the top surface of the wafer is polished or planarized to create a flat surface.

The CMP tool is comprised a rotating platen, slurry, pad, holding ring, brush, and pad conditioner. The mechanical element of this system applies downward pressure to a wafer surface, while the chemical reaction increases the material removal rate. The value chain of the CMP market consists of different players, including semiconductor material suppliers, CMP integrated solution providers, semiconductor wafer suppliers, semiconductor device manufacturers, slurry & pad manufacturers, technology solution providers, and CMP equipment manufacturers.

While CMP is still used for its traditional polishing applications for interlayer dielectrics, it’s also finding employment in more advanced applications, such as bulk oxide polishing, shallow trench isolation, “stop on poly” isolation, and polishing of various dielectrics in advanced transistor designs.

According to a recent market research report published by MarketsandMarkets, the global CMP market is expected to reach $4.94 Billion by 2020, at an estimated CAGR of 6.83% from 2015 to 2020.

Though the CMP market is at the mature stage, it still continues to evolve depending on the end users. The industry is being forced to adopt much innovation in process technologies and applications; as a result, different CMP processes have been evolved with technology nodes and newer applications such as MEMS, advanced packaging, and advanced substrates.

Applied Materials, Inc. (U.S.) and Ebara Corporation (Japan) are the major CMP equipment suppliers. Phoenix-based Entrepix offers unique CMP foundry services.

CMP includes consumable products, polishing pads and slurries. This CMP consumables market is dominated by major market players such as Cabot Microelectronics Corporation (U.S.), Fujimi Incorporated (Japan), and Dow Electronic Materials (U.S.).

Success in CMP lies in optimizing the many process variables. In addition to wafer variables such as film type and pattern density, CMP variables include: time, pressure (force applied to the wafer and pad), velocity, temperature, slurry feed rate, polishing motion, slurry chemistry and pH potential, slurry particle size, pad elasticity, pad hardness and pad condition method. An optimized CMP process also depends on removal rates of the film being planarized, adhesion stability of the film, minimal defects such as scratchs or pits, minimal corrosion (in the case of Cu), and the adhesion of organic or inorganic surface residues formed during the CMP process.

With alternate channel materials on the horizon for future logic transistor, III-V materials such as gallium-arsenide (GaAs), gallium-indium-phosphide (GaInP), and indium-phosphide (InP) are now in R&D which leads to questions regarding direct process costs as well as indirect EHS costs. Much of the concern involves the possible reaction and release of toxic hydrides such as arsine, and phosphine. SEMATECH worked with imec to monitor hydrides produced during CMP processes for high-mobility compound semiconductors.

Suggested Additional Reading:

Chemical Mechanical Planarization: Historical Review and Future Direction

Northern California Chapter of American Vacuum Society: CMP Users Group

CMP Technology Evolving to Engineer Surfaces

Reduced defectivity and cost of ownership of copper CMP cleans

Safe CMP slurries for future IC materials

The rule of three

Feed-forward can be applied for controlling overlay error by using Coherent Gradient Sensing (CGS) data to reveal correlations between displacement variation and overlay variation.

BY DOUG ANBERG and DAVID M. OWEN, Ultratech, San Jose, CA

As the semiconductor industry is fast approaching 10nm design rules, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge requiring overlay control to a few nanometers. There are many factors that impact the overlay budget that can be broadly categorized as those arising from the reticle, the lithography tool and wafer processing. Typically, overlay budget components associated with the reticle and lithography tool can be characterized and are relatively stable. However, as published elsewhere, process-based sources of surface displacement can contribute to the lithography overlay budget, independent of the lithography process (e.g., etch, anneal, CMP). Wafer-shape measurement can be implemented to characterize process-induced displacements. The displacement information can then be used to monitor specific processes for excursions or be modeled in terms of parameters that can be fed-forward to correct the lithography process for each wafer or lot.

The implementation of displacement feed-forward for overlay control requires several components, including: a) a system capable of making comprehensive surface displacement measurements at high throughput, b) a characterization and understanding of the relationship between displacement and overlay and the corresponding displacement variability, c) a method or system to integrate the displacement information with the lithography control system. The Coherent Gradient Sensing (CGS)technique facilitates the generation of high-density displacement maps (>3 million points on 300mm wafers) such that distortions and stresses induced shot-by-shot and process-by-process can be tracked in detail. This article will demonstrate how feed forward can be applied for controlling overlay error by using CGS data to reveal correlations between displacement variation and overlay variation.

High-speed, full-wafer data collection

Historically, patterned wafer surface inspection was limited to monitoring topography variations within the die area and across the wafer with the use of point-by-point measurements with low throughput, typically limiting measurements to off-line process development. Surface inspection of patterned wafers involving transparent films (e.g. SiO2 deposited films) was typically further limited to contact techniques such as stylus profilometry.

With CGS interferometry, a high-resolution front-surface topography map of a full 300 mm patterned wafer can be obtained for product wafers with an inspection time of a few seconds. Transparent films can typically be measured successfully without opaque capping layers due to the self-referencing attribute of the CGS interferometer. Essentially, CGS technology compares the relative heights of two points on the wafer surface that are separated by a fixed distance. Physically, the change in height over a fixed distance provides slope or tilt information and the fringes in a CGS interference pattern are contours of constant slope. In order to reconstruct the shape of the surface under investigation, interference data in two orthogonal directions must be collected. The slope data derived from the interference patterns is integrated numerically to generate the surface shape or topography. In-plane surface displacements in the x- and y-directions can then be computed from the surface topography using fundamentals of plate theory (FIGURE 1).

Fig 1-a Fig 1-b Fig 1-c

FIGURE 1. Example of the analysis of the uniform and non-uniform stress components of the displacement field: (a) total displacement computed from the x-direction slope, (b) uniform stress component of the displacement field determined from the best-fit plane to the data in (a), (c) non- uniform stress component of the displacement field.

To best utilize the capabilities of CGS technology for determining stress-induced displacement impacting critical layer overlay budgets, a “Post minus Pre” inspection strategy is typically employed, where two measurements of a wafer are taken: one prior to the process step or module of interest (the pre-process map), and a second measurement is taken on the same wafer after completing the process step or module (the post-process map). The pre-process topography map is then mathematically subtracted from the post-process topography map, providing detailed, high resolution information about the topography variation in the process step or module of interest. A series of topography maps illustrating the “Post minus Pre” process is shown in FIGURE 2.

FIGURE 2. Example of “Post minus Pre” topography CGS measurement.

FIGURE 2. Example of “Post minus Pre” topography CGS measurement.

The surface displacements directly impact the relative position of all points on the wafer surface, leading to potential alignment errors across the wafer at the lithography step. By measuring the evolution of process-induced stresses and displacement across multiple steps in a process flow, the overlay error due to the accumulated stress changes from those process steps can be evaluated, and the cumulative displacement can be calculated. The displacement error can then be fed forward to the lithography tool for improved overlay correction during the exposure process.

In the simplest implementation of this approach, the pre-process or reference measurement would be made following the prior lithography step, whereas the post- processing measurement would be made just before the lithography step of interest. In this manner, the total displacement induced between two lithography steps can be characterized and provided to the lithography system for overlay correction.

Stress and displacement process fingerprinting

By using CGS-based inspection to generate full-wafer topography, displacement and stress, detailed information can be provided for both off-line process monitoring (SPC), or in-line, real-time monitoring (APC) of process steps with significant process induced stress and displacement. A key consequence of the monitoring flexibility afforded by the measurement is the ability to characterize and compare within- wafer displacement and stress fingerprints of individual process chambers in a manufacturing line.

Target-based overlay metrology systems have historically been used as the only metrology tool to measure overlay error at critical lithography layers. Overlay data from the target-based overlay tools is collected after the wafer exposure step and is fed-backward to correct for the measured overlay error for subsequent wafers. As process- induced displacement errors are becoming a significant percentage of the layer-to-layer overlay budget, this post processing feed-back approach for overlay correction may not be sufficient to meet critical layer overlay specifications. Furthermore, overlay errors are often larger near the edge of the wafer where traditional overlay metrology target densities are typically low, providing only limited data for overlay correction.

The implementation of displacement feed-forward overlay correction can be
used to account for wafer-to-wafer and within-wafer distortions prior to lithography. The displacements can be characterized using an appropriate model and the model coefficients, or correctables, can be provided to the lithography tool for adjustment and control on a wafer-by-wafer basis. As shown in FIGURE 3, the CGS technique has the additional advantage of providing high-data density near the edge of the wafer (typically > 75,000 data points beyond 145 mm, sub-sampled in the Fig. 3 vector map for clarity), such that more accurate corrections can be determined where the overlay errors tend to be largest. As a result, lithography rework can be reduced and productivity increased. Case studies have revealed that a significant improvement in overlay can be achieved using this approach.

FIGURE 3. Vector displacement map showing process-induced edge distortion.

FIGURE 3. Vector displacement map showing process-induced edge distortion.

For each critical lithography step, a correlation is typically generated by comparing the traditional overlay measurement tool results to the surface displacement measured by the CGS measurement tool. Recognizing that displacement is only one component of the total overlay measurement, correlation of overlay to displacement requires effort to model or characterize the non-displacement components of the measured overlay. As a result, the appropriate correlation is derived by comparing total overlay to displacement plus the non-displacement overlay sources.

FIGURE 4 shows plots of total overlay versus displacement plus modeled non-displacement overlay sources for multiple locations on a single wafer processed in a leading-edge device flow. Figure 4a shows the x-direction data, whereas Fig. 4b shows the y-direction data. The data is presented in arbitrary units, however the same reference value in nanometers was used to normalize each set of data. The displacement data was evaluated at the same locations as the overlay target positions. For both the x-direction and y-direction data, the point-to-point correlation indicates good correlation with the correlation coefficients of 0.70 and 0.76, respec- tively. The RMS of the residuals of the linear fit to each data set are on the order of 1.5 to 2.0 nm.

Fig 4a

Fig 4b

FIGURE 4. Within-wafer (point-to-point) correlation of conventional overlay data and displacement data for the (a) x-direction and (b) y-direction.

FIGURE 5 similarly shows the wafer-to-wafer variation for overlay and displacement for the x-direction (Fig. 5a) and y-direction (Fig. 5b). The data in Fig. 5 are from multiple lots for the same lithography process evaluated to generate the data in Fig. 4. As with the point-to-point data, the wafer-to-wafer data shows strong correlation with correlation coefficients of 0.94 and 0.90 for the x-direction and y-direction, respectively.

Fig 5a Fig 5b

FIGURE 5.Wafer-level correlation between conventional overlay, |mean| + 3 sigma and displacement, |mean| + 3 sigma for a leading-edge process in the (a) x-direction and (b) y-direction.

The data in Figs. 4 and 5 illustrate key points regarding the correlation of overlay to displacement. First, the inherent variability of an advanced lithography process is typically on the order of 1 to 2nm. As a result, it is reasonable to conclude that the most of the scatter shown in Fig. 4 is likely associated with the variability in non-displacement sources of overlay variation. Second, the modeling or empirical characterization of non-displacement overlay sources is useful to the extent to which those non-displacement sources are constant. Consequently, if such modeling is part of the displacement feed-forward scheme in an effort to predict overlay, the model must account for known variations in the lithography process. A simple example is varia- tions in overlay performance due to differences between lithography chucks.

Displacement feed forward

It has been shown elsewhere that stress induced displacement can account for a significant fraction of the overlay error for certain critical layers at the 40nm node and below. It is therefore critical to develop the tools necessary for utilizing the measured displacement data for real-time in-line feed forward overlay correction to the scanner. One approach to this solution is to develop a system that allows the user to define the level of correction to be applied to the scanner for each lot, wafer or within-wafer zone.

FIGURE 6 shows a simplified schematic for a combined displacement feed-forward and image placement error feed-back approach. Once the process induced displacement for a specific set of process steps has been measured and correlated to overlay error, the measured displacement can be “fed forward” to the scanner in combination with traditional image placement error feedback techniques to further improve critical layer scanner overlay results. This approach is currently being implemented in leading-edge memory fabs to further reduce overlay errors on critical lithography levels and improve overall device yield.

Summary

The measurement of process-induced surface displacement can be an effective part of the overlay control strategy for critical layers at leading edge process nodes. CGS technology provides a method to comprehensively measure these displacements at any point in the process flow. Using a full-wafer interferometer, this system measures the patterned wafer surface in a few seconds and provides a map with up to 3,000,000 data points. This enables 100% in-line monitoring of individual wafers for in-situ stress and process induced surface displacement measurements. Its self-referencing interferometer allows the inspection to be made on any type of surface or films stack, and does not require a measurement target. This capability is currently being employed in numerous leading-edge memory and logic processes.

DOUG ANBERG currently serves as Ultratech’s Vice President of Advanced Lithography Applications; DAVID M. OWEN has been the Chief Technologist for Surface Inspection at Ultratech since 2006. Prior to joining Ultratech, Dr. Owen spent nearly a decade as a research scientist at the California Institute of Technology (Caltech) in Pasadena, and was the Founder and Chief Technology Officer for Oraxion Diagnostics.

It is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating.

BY KEITH BEST, Rudolph Technologies, Wilmington, MA, and PHILLIP HOLMES, TEL NEXX, Billerica, MA

Recent years have seen rapid development in the area of advanced packaging. In general, advanced packaging processes are concerned with the interconnection of multiple chips in a single package to provide increased functionality and performance in a smaller volume. System Scaling Technology — the combination of front-end, middle-end and back-end to advance microelectronic systems—utilizes many different advanced packaging approaches, one of which is known as 2.5D packaging. The term “2.5D packaging” has not always been used consistently in literature. The definition used for the purpose of this paper can be summarized as follows: a 2.5D package utilizes an interposer between multiple silicon die and a system-in-package (SiP) substrate, where this interposer has through vias connecting the metallization layers on its front and back surfaces (FIGURE 1).

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

 

The development of these new packaging schemes is being driven primarily by the rapid growth in mobile handheld devices such as smartphones. Often, the manufacturing processes used are adaptations of well-established front-end processes. A number of different approaches are in development or already in production, including wafer-level chip scale packaging, copper pillar bumps on through silicon vias (TSVs), fan-out wafer level processing, and many more. Of particular interest is the replacement of solder bumps by fine pitch copper pillar bumps, which has been the subject of many new system- in-package designs. Here we investigate the lithography and plating of copper pillars, with focus on heights in excess of 100μm and diameters of 25μm, in anticipation of future SiP requirements.

The increase in the number of I/O channels required by multi-chip system designs has exceeded the density and pitch capabilities that traditional solder bump processes can deliver, so that an alternative connection scheme is required. For interposers, the key enabling technology has been the development of fine pitch copper pillar bumps to provide the high-density interconnection between the interposer and the die. Copper pillar bumps provide a number of advantages over the solder bumps they are supplanting. They can deliver finer pitches, 40μm and less have been demonstrated. They also provide superior electromigration performance in applications where high current-carrying capacity is required. However, lithography and electroplating for fine pitch copper pillar bumps can be particularly challenging. The pillars are electroplated into openings in a thick layer of photoresist which exceeds the capability of most front-end tools. Typically, today’s copper pillars range from 30-50μm in height, with height to width aspect ratios from 1:1 to around 2:1 Here we describe the lithography, resist, and electroplating systems and processes required to create 5:1 aspect ratio copper pillars with heights in excess of 100μm.

Photoresist

A negative tone photoresist (JSR THB-151N) was chosen for this work. Its acrylate groups cross-link on exposure and are developed in industry standard 2.38% TMAH developer. The photoresist was spun to a thickness of 120μm on 300mm silicon wafers with an under bump metallization (UBM) prepared seed layer. To reach the 120μm photoresist film thickness, two coatings of photoresist were required, soft baked at 130C, 300secs and 130C, 360secs respectively. After coating, the photo- resist film was allowed to rehydrate for one hour prior to exposure on a wafer stepper (Rudolph Technologies’ JetStep System).

Lithography

We used a customized test reticle that included a wide range of sizes and pitches to expose the wafer. When processing a thick photoresist, well-controlled sidewall angles are a critical requirement, especially when electroplating tall copper pillars. Most front-end tools have high numerical aperture (NA) lenses with low depth of focus (DOF) that prevent adequate exposure of thick films with sufficient image contrast to meet the sidewall angle and resolution requirements. Mask aligners also struggle with high aspect ratio imaging, not because of their NA, but because they are unable to provide the necessary focus offset required to expose the film at high resolution, ultimately limiting their aspect ratio and sidewall angle control. Although photoresist sidewall angles are primarily a function of the photoresist material and its processing (pre-bake, post-bake, developing, etc.), the exposure system plays an important role. Accurate focus control across the wafer or substrate is required to achieve consistent and accurate CD control with straight and perpendicular sidewalls.

The lithography stepper employed in this study refocuses for each exposure to ensure optimal focal plane height on advanced packaging substrates that are frequently warped by film stress and thermal cycling. The system’s 0.1 NA provides a large depth of focus to maintain image integrity and CD control through thick films. The stepper lens is achromatized and the installed “filter wheel” provides a choice of illumination wavelengths to expose the photoresist layers: “broadband” ghi (350-450nm), gh (390 to 450nm) or i-line (365nm). This study, with a photoresist thickness of 120μm, required high energy illumination of >1000 mJ/cm<sup>2</sup>, so broadband illumi- nation (g,h,i wavelengths) was employed to maintain high throughput.

The coated wafers were exposed using a focus exposure matrix wafer layout which provided a large number of programmed focus and exposure conditions at a fixed stepping distance to enable quick and efficient character- ization of the lithography process window for any pillar CD. After exposure, the wafers were developed for a total time of 180 secs, using 6 puddles in 2.38% TMAH. A number of wafers were processed in this way to provide images of the resist structures prior to the electroplating process. The SEM micrograph in FIGURE 2 shows a cross section of the photoresist via mold structures, the CD limit appears to be 25μm with this process, since the via is not open to the seed metal beyond this resolution.

lithography 2

It is interesting to note how the sidewall angle of the photoresist changes with decreasing CD suggesting that the plating will generate a “pedestal” type of copper pillar base at larger CDs, becoming progressively more vertical at smaller CDs. However, upon closer inspection of the smallest CDs, a slight “footing” can be observed at the base of the via (FIGURE 3), and this could result in slight undercut of the final copper pillar. The footing effect was most likely the result of our unoptimized develop process.

lithography 3

Electroplating

After the lithography processing, the wafers were sent to TEL NEXX for electroplating. The plating process employed the TEL NEXX Stratus P300 System, a fully automated electrochemical deposition system for advanced wafer-level packaging applications. The system deposits thick metal layers for wafer bumping, redistribution layers, TSVs, integrated passives, and MEMS.

In this study, we used a methanesulfonic acid copper chemistry with organic additives. The bath composition, operating temperature and current waveform were optimized for high speed copper plating into very thick resist features with flat bump profiles. After plating the photoresist was stripped using an immersion bath with EKC162 solution at 60 degrees. To preserve the profile of the photoresist mold the seed layer was not etched. The final copper pillar structures exhibit the inverse photo- resist mold profile (FIGURE 4).

lithography 4

The electroplating process successfully deposited copper in the photoresist via “molds” that were open to the copper seed material, producing good quality copper pillars with a final minimum copper pillar CD of 20μm, indicating a process bias of 5μm. This bias enabled the final copper pillar to reach a 6:1 aspect ratio as shown in FIGURE 5.

lithography 5

The final copper pillars exhibit excellent sidewall angle, 90 degrees for the smaller CDs. The profiles correlate well with the profiles observed in the photoresist SEM cross sections. The change in profile at the base of the photoresist for the smaller CDs did result in a slight undercut of the final copper pillar. The removal of this photoresist foot could be achieved by either increasing the de-scum time or modifying the develop recipe. The larger copper pillars tended to flare out slightly at the base (FIGURE 6) compensating for any undercut. This will benefit the structure during the removal of the copper seed layer.

lithography 6

The rheology of the copper pillar surface is very important for bonding reliability and the uniform plating of Sn solder, which was not performed during this particular study since it was not the primary objective. FIGURE 7 shows the flat top surface of a copper pillar which is free of voids and defects.

lithography 7

For advanced packaging applications, precise copper pillar height control is essential, and lithography CD control plays an important part in the plating process since CD variation directly affects plated height. The electroplating rate is proportional to current per unit area, i.e. the open area at the bottom of the photoresist openings at the beginning of the process, and the area of the evolving metal surface during deposition. Variation in CD or sidewall angle across the wafer will result in a corresponding change in copper pillar height. For example, in the case of copper pillar features a 5% change in CD can cause a 10% change in plated height.

Conclusion

The results of this study prove that it is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating. As advanced packaging requirements continue to evolve, the ability to create smaller copper pillar CDs at finer pitches in thick films will provide increased I/O density opportunities for SiP designers. Furthermore, it is clear that achieving high yield and reliability in the final package requires precise CD control throughout the entire photoresist profile to ensure consistent copper pillar height.

KEITH BEST is director applications engineering at Rudolph Technologies, Wilmington, MA. PHILLIP HOLMES is director of technology at TEL NEXX, Billerica, MA

Vistec Electron Beam GmbH, a supplier of electron-beam lithography systems, announced that it has established a show room facility in Schaumburg, IL to promote and demonstrate their Variable Shaped Beam systems specifically for the US and North America market.

The show room facility in Schaumburg is designed to demonstrate the functionality and operation of Vistec’s ebeam equipment and to provide an insight into its various applications. The key component of the facility is a fully operational Vistec SB254 electron-beam lithography system, installed in a clean room of 970sqft., supplemented by a set of process and measurement equipment for standard sample processing.

“We are very pleased to be able to offer such a demonstration capability to potential North America market customers. The availability of the show room facility shall manifest our commitment to this important high technology region, it will foster our activities to better understand customer needs and shall help to provide tailored solutions to their specific requirements,” said Wolfgang Dorl, General Manager of Vistec Electron Beam.

The availability of patterning alternatives in the lithography landscape represents a big opportunity to properly address the coming needs generated by the IoT.

BY LAURENT PAIN, RALUCA TIRON, LUDOVIC LATTARD, STEFAN LANDIS and CYRILLE LAVIRON, CEA-Leti, Grenoble, France

The Internet of Things (IoT) is expected to fuel significant growth opportunities for the semiconductor industry, as demand increases for wireless components and more and more embedded functionalities such as memory and sensors. This growth will affect almost all integrated circuit (IC) sectors (FIGURE 1). The chip industry will continue to need advanced technologies to provide the most powerful functionalized ICs with lower power consumption for the IoT, but manufacturing costs remain a key challenge. Lithography and related patterning technologies can represent up to 50 percent of total IC production costs, and significant efforts have to be made in the coming years to slow and even reverse this trend.

Litho Fig 1

In the lithography landscape for the development of advanced technology nodes, extreme-UV (EUV) lithography technology recovered some credibility at the beginning of 2015 with the release and installation of the first 80W power sources[1]. However, its adoption by the industry remains uncertain, because its infrastructure still requires significant development. Also, the recurrent questions about the real cost of ownership associated with the ability of the 0.33NA platform to address sub-7nm technology nodes continue to dominate the debate in the semiconductor community, especially since 3D-stacking strategies are being seriously investigated. This potentially could slow demand for high-resolution and therefore delay the new advanced lithography solutions.

Meanwhile, 193nm immersion lithography, with double- or quadruple-patterning strategies, supports the industry preference for advanced-node developments, despite the tremendous effort required for process controls (alignment, mask manufacturing etc.). In this landscape, lithography alternatives maintain promise for continued R&D because they may present competitive compromises for the industry. Massively parallel electron-beam and nano-imprint lithography techniques remain highly attractive, as they can provide noteworthy cost-of-ownership benefits for IC manufacturers. In addition, directed self-assembly (DSA) lithography with block copolymer shows promising resolution capabilities and appears to be an option to reduce multi-patterning strategies, and therefore the associated mask-set budgets. But what is the current status of these technologies? Are they really able to meet industry expectations for advanced technology nodes? Are they indeed able to reduce manufacturing costs? What are their introduction points into the production environment?

CEA-Leti is working to answer these questions and has initiated collaborative R&D programs to assess and boost the development of these alternative technologies through strategic partnerships. Three programs have been launched with the primary goals of demonstrating that these lithography options can meet industry needs, assessing industrial use of them and proposing to Leti’s IDM partners real turn-key integrated process-flow solutions.

  • IMAGINE: launched in 2009 with MAPPER Lithography, this program is pushing for the insertion of massively parallel direct-write electron-beam technology. Other participants include TSMC, STMicroelectronics, Nissan Chemical, Mentor Graphics, SCREEN, Tokyo Electron and Aselta Nanographics.
  • IDEAL: DSA lithography represents a promising solution for advanced patterning. Leti has worked with Arkema since 2011 on the qualification and demonstration of materials for insertion into industrial production flow. Other partners include ST, Tokyo Electron, SCREEN, Mentor Graphics and CNRS-LCPO.
  • INSPIRE: established in 2015 with the EV Group, this program will focus on the assessment of imprint technology on large-scale patterning.

Directed self assembly: the resolution is in polymer matrix

Since 2010, DSA has steadily attracted attention of R&D laboratories and the IDM industry. The natural high-resolution capability of the block copolymer (sub-10nm) may meet the requirements of future technology nodes. Significant work in this area is underway at R&D consortia such as imec, IBM Research in Albany, N.Y., and Leti, as well as directly in the fab[2,3]. For example, Leti and its partners put in place a full infrastructure to qualify the new material developed by the chemical company Arkema (FIGURE 2). A full 300mm line is operational at Leti using a Tokyo Electron track and a customized SCREEN DUO track able to handle the latest process possibilities. This type of infrastructure is required to validate in fab-like conditions the new materials (PS-PMMA and high chi platforms) and their associated integration flows. Those operating conditions give industry the capability to quickly evaluate the full process-flow performances with all the required classic statistical data for final validation.

Litho Fig 2

Focusing on defectivity Intel showed convincing data at 1def/cm2 on line-and-space structures, confirming the potential of DSA to reach the ITRS target and therefore to be used for manufacturing in the near future (FIGURE 3). As well, Leti results on grapho-epitaxy process are also very encouraging with zero visual-defect process flow for contact/via application measured with low statistical level[4]. Those results are the first positive key trends in the DSA technology. Evaluating the compatibility of DSA with semiconductor process flows is the next important step. The control of the iso-dense configuration focused a lot of attention on the grapho-epitaxy process, in which block copolymer film-filling uniformity is affected by the topography effects of the guide patterns. Leti developed and patented a flow allowing a proper control of CD and CDU in all density configurations. (FIGURE 4) This solution preserves the interest of DSA as it is integrated in the process flow itself and because it does not imply a need for any additional design-rule restriction[4].

Litho Fig 3

Nevertheless, some hurdles remain to be overcome before its final adoption. The control of the surface affinity is one key aspect. It can greatly affect the final defectivity level and impact the complexity of the integration flow (FIGURE 5). Any non-uniform control of the bottom residual polymer thickness in the bottom of the guide cavity may lead to post-etch opening issues and final circuit-yield drop. Moreover, to be fully adopted, DSA technology also must be aligned with the compatible design rule manuals. Insertion in the DRM is essential and it implies adding new specific constraints due to the nature of the block copolymer and to the lithography guide realization. All these R&D efforts must be pushed to value the advantages of DSA technology: the natural high resolution of this solution and its cost effectiveness from reducing multi-exposure strategy. In addition to ensuring DSA’s ability to extend 193nm immersion lithography,it also supports the use of the EUV 0.33NA tool for the development of 7nm nodes and below.

Litho Fig 4

Massively parallel electron-beam writing

Despite recurrent delays in new developments, parallel electron-beam lithography remains an attractive alternative option. The massively parallel writing solutions developed by MAPPER Lithography and IMS Nanofab-rication for wafer and mask writing, respectively, offer good compromises: a significant alliance of resolution and advantageous manufacturing costs. But this technology also benefits from additional advantages, such as writing flexibility and a significant throughput improvement due to the parallel exposure concept that can boost the throughput in the future up to 100 wafers per hour in a cluster-tool configuration. First pre-industrial units are today installed in pilot-line environments, foreshadowing their introduction into production lines in coming years.

MAPPER and Leti’s collaboration is focused on introducing this technology for direct-write application. This joint program started in 2009 around the MAPPER’s pre-alpha tool that validated the key concept of the MAPPER technology in terms of parallel writing and resolution capabilities (FIGURE 6). The partnership entered in a new phase in 2014 with the installation of the first FLX-1200 pre-production platform, (FIGURE 7), operating 1,300 beam lines for a targeted throughput of 1 wph and then scalable to 10 wph by increasing the beam line count up to 13,000.

Litho Fig 5 Litho Fig 6

This FLX-1200, which is being ramped up now, already has shown imaging performances that match its specifications. Full 300mm wafers can be printed in one hour with 32nm half-pitch resolution (FIGURE 8). In the IMAGINE program, Leti and its partners are also working to validate a complete turn-key integrated solution allowing fast and secure wafer processing from design to silicon. Such infrastructure developments around data treatment, materials, process, etch and metrology will be required to speed-up the insertion of the MAPPER technology into future production lines.

Litho Fig 7

Leti and MAPPER will demonstrate the operational capability of the FLX-1200 in its final configuration, including mix-and-match alignment performances. The achievement of this key demonstration milestone is essential to launching this technology. Then, after final ramp-up, the MAPPER platform is expected to be aligned in terms of specifications with 14nm technology (32nm hp). A wide range of potential applications based on its mask-less concept and throughput potential already have been clearly identified: CMOS prototyping and low-volume production, complementary lithography concept for high-end patterning[6], new industry segments (photonics, low-cost circuit functionalization, large field exposure, etc.).

Nano-imprint lithography

Nano-imprint lithography (NIL) stands out from the other conventional lithography processes (photo-lithography, electronic lithography, EUV lithography) because of the fundamental mechanism of creating the final structures. In the case of nano-imprint, the flow of the resist directly shapes the pattern through the stamp cavities, eliminating the need for chemical contrast, as is the case for optical lithography resists. In recent decades, significant efforts have been made to extend the distance between the photomask and the resist-coated wafer to reduce defectivity and enhance resolution. Therefore, for many scientists, NIL technology appeared to be a UFO, since the process is based on the intimate contact between the working stamp and the resist to be embossed.

In the past 20 years, significant progress has been made to make the technology more mature and ready for high-volume manufacturing. Among the several existing NIL technology alternatives, the UV-based imprint, using transparent stamp, is today the standard one. Two well-established options are now available on the market: the full-wafer imprint (the size of the stamp corresponds to the size of the wafer to be printed) and the step-and-flash imprint in which a small stamp (i.e. die size) is stepped, as in optical lithography across the wafer to be processed (FIGURE 9).

Litho Fig 8

If the step-and-flash NIL technology is better suited to address the semiconductor markets (NAND flash memory, DRAM and logic) with its high level-alignment capability and its good control of defectivity density[7], the full-wafer NIL option could quickly become the reference manufacturing option for the emerging and growing markets such as LED and photonics-based devices (FIGURE 10).

Litho Fig 9

However, this wafer-scale imprint solution still lacks quantitative data regarding its technology assessment for high-volume manufacturing. Commercial equipment[8] and resists, the cornerstones of this technology, are already available. But some links in the industrial supply chain (design rules, master manufacturing and repair, in-line defectivity and metrology controls, fully integrated process flows) still must be established and qualified to make this technology more mature.

To accelerate adoption of this technology, Leti and EV Group launched in June 2015 a new collaborative industrial program called INSPIRE, aimed at demonstrating the benefits of this full-wafer NIL technology and spreading its use for applications beyond the traditional semiconductor industry. Much more than a classic industrial partnership, the program is designed to support development of new applications from the feasibility-study stage up to the first manufacturing steps, including the prototyping phase in Leti’s clean room. INSPIRE is also designed to demonstrate the technology’s cost-of-ownership benefits for a wide range of application domains. The final objective of this program is to facilitate the transfer of the developed integrated process solutions to industrial partners. The steps should significantly lower the entry barrier for NIL technology and speed up its use in production lines.

Conclusion

The availability of patterning alternatives in the lithography landscape represents a big opportunity to properly address the coming needs generated by the IoT. Besides conventional optical lithography, they offer industry new and/or complementary advantages: innovation capability and opportunities to better manage cost of ownership. But not only that! The high-resolution potential, the ability to facilitate design-innovation validation, and the complementarity of these alternatives with other patterning solutions also highlight their strengths. The step now is to finalize the evaluation of these technologies with respect to industry standards and establish them as real and credible lithography alternatives.

References

1. A. Schafgans et al, Proc SPIE, Extreme Ultraviolet Lithography VI, Vol. 9422, 2015
2. S. Sayan et al, Proc. SPIE, Advances in Patterning Materials and Processes XXXII, Vol. 9425, 2015
3. H. Tsai et al, ACS nano, vol 8 (5), pp. 5227-5232, 2014
4. R. Tiron et al, Alternative Lithographic Technologies II, Vol. 9423, 2015

SAN JOSE, Calif. — Nov. 11, 2015 — Ultratech, Inc., a supplier of lithography, laser-processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HB-LEDs), as well as atomic layer deposition (ALD) systems, today introduced the Superfast 4G+  in-line, 3D topography inspection system. Ultratech’s new 4G+ system builds on the field leadership of the Superfast 4G, providing the industry’s highest-productivity and lowest-cost solution for high-volume manufacturing. The Superfast 4G+ system’s patented coherent gradient sensing (CGS) technology enables Ultratech customers to use a single type of wafer inspection tool to measure patterned wafers across the entire fab line at the lowest cost. Ultratech plans to begin shipping the Superfast 4G+ systems in the first quarter of 2016.

Superfast 4G+ features include:

  • Direct, front-side 3D topography measurement for opaque and transparent stacks patterned wafers
  • 150 wph, the highest industry 3D in-line inspection throughput with the smallest footprint
  • 1-mm edge exclusion enabling full-wafer pattern inspection and thin-film 3D process control
  • Large bow option for in-line manufacturing control of highly bowed wafers without impacting throughput

Damon Tsai, Ultratech Asia Director for Inspection Systems, said, “Our current leadership position in in-line 3D inspection at advanced memory and foundry manufacturers with Superfast 4G has provided us with a tremendous learning environment. Our partners have helped us develop new hardware capabilities like the ‘Recipe Driven Range Control,’ an innovative high-throughput, large bow optical option on board the Superfast 4G+, as well as new fleet management performance metrics. The inherently simple design of the CGS technology is enabling us to rapidly deliver new capabilities and performance improvements over more complex optical solutions.”

Based on patented CGS technology, Ultratech’s Superfast 4G+ inspection system provides the industry’s highest throughput (150 wph) with the lowest cost-of-ownership compared to competing systems. The direct, front-side 3D topography measurement capability is well-suited for patterned wafer applications such as lithography feed-forward overlay distortion and edge-defocus control as well as thin-film deposition stress and planarization control. Delivering a 2X improvement in performance with fleet matching TMU (Total Measurement Uncertainty), along with the ability to measure opaque and transparent stacks on patterned wafers, the Superfast 4G+  provides cost-effective technology to address the critical needs of its global customers. In addition, leveraging the same breakthrough CGS optical module, the Superfast 4G+ is available as a field upgrade of the Superfast 4G.