Category Archives: Resource Guide

According to a new market research report on the “Chemical Mechanical Planarization Marketby type (Equipment & consumables), Application(IC manufacturing, MEMS & NEM, Optics and Others), Technology (Leading edge, More Than Moore’s, and Emerging), and Geography (North America, Europe, APAC and RoW) – Global Forecast to 2020”, published by MarketsandMarkets, the market is expected to grow at a CAGR of 6.83% between 2015 and 2020, and reach $4.94 Billion by 2020.

Chemical mechanical planarization is a critical process technology step in the semiconductor wafer fabrication process. In this process step, the top surface of the wafer is polished or planarized to create a flawless flat surface that is essential to make faster and more powerful semiconductor devices with the aid of chemical slurry & mechanical movements. The CMP tool is comprised a rotating platen, slurry, pad, holding ring, brush, and pad conditioner. The mechanical element of this system applies downward pressure to a wafer surface, while the chemical reaction increases the material removal rate. The value chain of the CMP market consists of different players, including semiconductor material suppliers, CMP integrated solution providers, semiconductor wafer suppliers, semiconductor device manufacturers, slurry & pad manufacturers, technology solution providers, and CMP equipment manufacturers.

The global Chemical Mechanical Planarization Market was worth USD 3.32 Billion in 2014, and it is expected to reach USD 4.94 Billion by 2020, at an estimated CAGR of 6.83% from 2015 to 2020. Though the CMP market is at the mature stage, it still continues to evolve depending on the end users. The industry is being forced to adopt much innovation in process technologies and applications; as a result, different CMP processes have been evolved with technology nodes and newer applications such as MEMS, advanced packaging, and advanced substrates. The growing demand for consumer electronic products, increasing need of wafer planarization, and increasing use of micro-electro-mechanical systems (MEMS) is driving the global CMP market.

The CMP equipment market is expected to grow at the highest CAGR of 8.32% from 2015 to 2020. The key factors behind the high growth of the CMP equipment market is the strong growth in semiconductor equipment and capital spending. The CMP consumables market was valued at USD 2.25 Billion in 2014 and is expected to reach to USD 3.21 billion by 2020. The Applied Materials, Inc. (U.S.) and Ebara Corporation (Japan) are the major CMP equipment suppliers for different integrated device manufacturers.

This CMP consumables market is dominated by major market players such as Cabot Microelectronics Corporation (U.S.), Fujimi Incorporated (Japan), and Dow Electronic Materials (U.S.).The CMP regional market is mainly dominated by Asia-Pacific, followed by North America and Europe. The Asia-Pacific region accounted for the largest market share of ~67% and is expected to grow at the highest CAGR of 7.40% during the forecast period, followed by North America. The countries in Asia-Pacific region such as Taiwan, South Korea, Japan, and China are investing more in semiconductor manufacturing to meet the increasing demand for consumer electronic products. This detailed market research study provides detailed qualitative and quantitative analysis of the global chemical mechanical planarization market. It provides a comprehensive review of major market drivers, restraints, opportunities, challenges, and key issues in the market.

The eBeam Initiative, a forum dedicated to the education and promotion of new semiconductor manufacturing approaches based on electron beam (eBeam) technologies, today announced the completion of its fourth annual eBeam Initiative members’ perceptions survey. A record 64 industry luminaries representing 35 different companies from across the semiconductor ecosystem–including chip design, equipment, materials, and manufacturing, as well as photomasks–participated in this year’s survey. The eBeam Initiative also completed its first-ever merchant and captive mask makers’ survey. In related news, ZEISS, a company in lithography optics for semiconductor manufacturing, has joined the eBeam Initiative.

Among the results of the members’ perception survey, respondents expressed increased optimism in the implementation of EUV lithography for semiconductor high-volume manufacturing (HVM) compared to last year’s survey, while at the same time acknowledging that EUV lithography is expected to add greater complexity to photomask manufacturing. In addition, expectations on the use of multi-beam technology for advanced photomask manufacturing continue to remain strong. Results from the eBeam Initiative’s first mask makers survey–which not only provides insight into the challenges and opportunities for photomask manufacturers but also gives mask makers a way to assess their own progress relative to their peers–indicate growing mask complexity across many fronts. The complete results of both surveys will be presented and discussed by an expert panel today during the eBeam Initiative’s annual members meeting at the SPIE Photomask Technology Conference in Monterey, Calif., and are available for download at www.ebeam.org.

Highlights from eBeam Initiative Member Survey

  • 62 percent of respondents predict that multi-beam technology will begin to be used for photomask production by the end of 2016 to address the critical problem of mask write times as the industry moves to smaller geometries.
  • Mask makers appear to be the most optimistic about the availability of multi-beam mask writers, with a near-unanimous 96 percent of mask makers participating in the survey indicating that multi-beam will be used for HVM mask writing by the end of 2018, compared to 65 percent of all equipment suppliers.
  • Among five next-generation lithography (NGL) technologies being considered for advanced semiconductor fabrication, respondents predict EUV as the most likely NGL method to be used in at least one manufacturing step by 2020, with an average confidence rating of 62%.
  • At the same time, 59 percent of respondents predict that EUV will drive the need for complex mask shapes.

Highlights from Mask Makers Survey (data from Q3 2014 through Q2 2015)

  • Mask sets below the 22-nm logic node are exceeding 60 masks for the first time, while mask sets have seen a long-term growth rate of 13 percent since the 250-nm node.
  • Average mask writes times have exceeded the nine-hour mark (9.6 hours) while the longest write time reported was 72 hours.
  • A strong majority (75 percent) of mask makers predict that they will modulate exposure dose on a per-shot basis in 2017.

“eBeam technology is critical to enabling the continuation of Moore’s Law, regardless of which lithography approach is used for semiconductor design and cost scaling,” stated Dr. Markus Waiblinger, senior product manager, strategic business unit Semiconductor Metrology Systems of ZEISS. “As an innovator in the use of eBeam technology for optical and EUV mask inspection, review and repair solutions, ZEISS applauds the eBeam Initiative for educating the semiconductor supply chain about new developments in eBeam technology and for providing a forum for greater collaboration. Efforts like the annual members’ survey and now their first mask makers’ survey play an important role in fulfilling that charter, and we’re pleased to have the opportunity to participate as a new member of the eBeam Initiative.”

“On behalf of the eBeam Initiative, I wish to thank all of our members–including our newest member ZEISS–for their participation in our fourth annual members’ perception survey,” stated Aki Fujimura, CEO of D2S, the managing company sponsor of the eBeam Initiative. “2015 has truly been an exciting year for the Initiative, as members of the eBeam community continue to step forward with new solutions to solve some of the semiconductor and photomask industry’s most pressing manufacturing challenges. Interest and excitement in eBeam technology continues to grow, which is reflected in the record turnout of responses that we received for our annual survey, as well as the strong reception from the global mask community toward our inaugural mask makers’ survey. Feedback from these surveys is invaluable in helping guide our education efforts within the eBeam supply chain, and we look forward to presenting our results for both surveys at the SPIE Photomask Conference later today.”

ULVAC, Inc. announced that it has recently developed and started selling the ECO-SHOCK ES4A, a power saving accessory for dry vacuum pumps that can reduce power consumption substantially by attaching to the dry vacuum pump exhaust line.

Dry vacuum pumps consume particularly large amounts of electricity in production lines. Therefore, it is important to reduce their power consumption. ULVAC has already released the ECO-SHOCK ES10, which reduces power consumption when attached to a dry vacuum pump exhaust line. However, it has been difficult to reduce power consumption of dry vacuum pumps that are used for frequent pumping down of loading/unloading chambers of vacuum systems and use large amounts of sealing gas. To resolve this difficulty, ULVAC has launched the ECO-SHOCK ES4A.

Features:

  • The ECO-SHOCK ES4A makes possible a substantial reduction in power consumption of dry vacuum pumps used for the following purposes: Dry vacuum pumps that are used for frequent pumping down of loading/unloading chambers; dry vacuum pumps that use large amounts of sealed gas.
  • There is no degradation of pumping speed because any control such as rotation speed adjustment is required when attaching it to dry vacuum pump. Also, even if the ES4A was broken down, there is no decrease in performance of dry vacuum pump.

The ECO-SHOCK ES4A can be attached to dry pump exhaust lines that have already been installed. It can be used to pump down air, nitrogen, argon and other stable and safe gases. However, it cannot be used in applications such as flammable, burn ability and toxic gas exhausts, or for solid/fluid suction. It can also be used for a dry vacuum pump, which does not affect performance when making exhaust port under vacuum.

By Pete Singer, Editor-in-Chief

Opportunities for cost savings abound in the “sub-fab” of semiconductor operations where the vacuum pumps and gas abatement systems

Dr. Michael Czerniak, Environmental Solutions Business Development Manager, at Edwards Ltd.

Dr. Michael Czerniak, Environmental Solutions Business Development Manager, at Edwards Ltd.

reside. Typically, these systems are running full tilt, no matter what’s going on in the process tool.

In a case where the cobbler’s children may finally be getting new shoes, work is underway to improve the communication between sub-fab equipment and process tools so that fuel in gas abatements systems can be turned off if there’s nothing to abate, and vacuum pumps can be throttled back or slowed if there’s nothing to pump.

“If you have equipment that is enabled with this capability, you can access these savings by essentially turning down the power or the fuel gas consumption when they’re not actually required for chip processing, said Dr. Michael Czerniak, Environmental Solutions Business Development Manager, at Edwards Ltd.

Czerniak gave a talk at 2:00pm on Tuesday at SEMICON West as part of the Sustainable Manufacturing Forum. The forum, held on Tuesday in Moscone North, Hall E, Room 132 from 10:00am to 5:00pm, allows experts to share the latest information on the environmental and social impacts of advanced technologies that are likely to be introduced into semiconductor manufacturing in the near future.

At SEMICON West in 2014, Czerniak was honored with SEMI’s Merit Award, along with Daniel Chlus (IBM) and Lance Rist (RistTex). The trio, were part of the Energy Saving Equipment Communication Task Force responsible for developing new standards designed to help reduce energy consumption in production equipment, specifically the SEMI E167 standard.

While production equipment and support equipment are all capable of reduced utility consumption, implementation has been slow due to lack of a standard.

SEMI’s E167 solved one piece of the puzzle – enabling the factory host to tell the process too that there are no wafers coming, for example – another standard is needed for the tool to communicate with sub-fab equipment that it, too, can power down. That is where a new standard, SEMI S23 comes in. “Once the tool has decided it doesn’t need pumps and abatement for the next 45 minutes or so — whatever it decides — it can then cascade that message down to the subfab where the energy savings will actually take place,” Czerniak explained.

At SEMICON West, a working group of the SEMI S23 task force is preparing additions to the Related Information section of SEMI S23 to provide for suggested utility-consumption test conditions and report formats for some components and peripheral equipment commonly used in semiconductor manufacturing equipment systems.

The components initially considered are dry vacuum pumps, refrigerated chillers and heat exchangers, although other components such as process power equipment may be considered soon. Also under discussion is the inclusion of Related Information for the application of efficiency rating systems for components and peripheral equipment. The goal of the working group is to produce suggested new Related Information in SEMI S23 for consideration on a future SEMI Standards Ballot.

“We’re working pretty hard as part of a SEMI standards committee – to get standardized signaling for that sort of information – so that all pump and abatement suppliers can get access to signals that allow them to do these energy savings,” Czerniak said.

Czerniak said this will work best in a new facility, once the tools have the ability to communicate directly with the pumps and abatement systems. In a retrofit scenario, it can be a challenge to get those signals. “We’re talking about getting signals derived from loadlock pumps,” he said.

In practice, it may be impossible to actually turn off vacuum pumps completely, particularly those that are pumping byproducts that tend to condense inside the pump. “You generally don’t want to switch them off due to the risk of not being able to restart them. In those cases, what you do is typically reduce the frequency at which you spin them and save maybe 10-15% of the running power. To get them back to full speed and full operating temperature isn’t such a long period of time,” Czerniak said.

On the other hand, with gas abatement systems, particularly those that burn fuel (i.e., natural gas) to destroy the byproducts, it’s possible to shut them to near zero. “In our case, we usually just leave them running on a pilot flame. They come back on line in tens of seconds, and you save about 90% of your fuel gas. There are very significant savings,” Czerniak said. “At the same time, you also save on your CO2 footprint. It gets to be quite an important factor when people do CO2 audits of their manufacturing process so they can put green stickers on their end products.”

This has been the focus of one of the working groups in the European EEM450PR project, which is focused on 450mm tool developed (similar work is underway at the G450C Consortium in Albany).

In his talk on Tuesday, Czerniak described those models that were constructed as part of the EEM450PR project to simulate the impact of green modes, at various levels of wafer inactivity, initially for 300mm, and then extended for a hypothetical 450mm fab. It was also noted that additional savings would be possible in the facility, e.g. reduced process cooling water when the pump and abatement thermal load is reduced. The model was then validated by looking at data from a HVM 300mm fab, simulating the effect of green modes (without actually implementing them), and also live green mode implementation on pumps and abatement at imec’s R&D lab in Europe.

A live demonstration was also conducted in the G450C Albany fab on some installed 450mm toolsets, as part of the complementary and collaborative engagement between the regions on the 450mm topic, in order to validate the assumptions for future 450mm fabs.

Applied Materials, Inc. today announced a next-generation etch tool, the Applied Centris Sym3 Etch system, featuring an entirely new chamber for atomic-level precision manufacturing. To overcome within-chip feature variations, the Centris Sym3 system leapfrogs current tools to provide chipmakers with the control and precision needed to pattern and create densely packed 3D structures in advanced memory and logic chips.

“Drawing on over 20 years of etch learning and our expertise in precision materials removal, the Sym3 system represents a brand new design, built from the ground up, that solves persistent and impending industry challenges,” said Dr. Raman Achutharaman, vice president and general manager of Applied’s Etch business unit. “Customer traction has been remarkable, resulting in the fastest adoption rate we’ve seen for an etch tool in the company’s history, with record ramp to production at leading-edge fabs.”

The Centris Sym3 etch chamber employs Applied’s True Symmetry technology with multiple tuning controls for optimizing global process uniformity to the atomic level. Key to the design is a focus on controlling and removing etch byproducts, which are increasingly hampering within-chip patterning uniformity. The system mitigates byproduct re-deposition to overcome the challenges of line edge roughness, pattern loading and defects – issues that are becoming more limiting for each successive technology node. Combined with an advanced RF technology that controls ion energy and angular distributions, the Sym3 system delivers unsurpassed vertical profiles for high aspect ratio 3D structures.

The Centris Sym3 platform’s six etch and two plasma clean process chambers feature system intelligence software to ensure that every process in every chamber matches precisely, enabling repeatability and high productivity for high-volume manufacturing. 

Applied Materials, Inc. develops engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries. 

By Jeff Dorsch, Contributing Editor

Plasma etching is a key step in wafer fabrication, from deposition to the patterning of photolithography to dry or wet etch. As such, it is a crucial and hotly-contested area for vendors of semiconductor manufacturing equipment.

Lam Research holds about half of the worldwide etch equipment market and principally competes with Applied Materials, Tokyo Electron, and Hitachi High-Technologies.

In May, Lam introduced the Kiyo F Series conductor etch system for volume production of advanced DRAMs and 3D NAND flash memory devices. Lam says the Kiyo F Series is employed for critical conductor etch applications at “all major memory manufacturers.”

A year ago, Lam brought out the 2300 Kiyo F Series with the Hydra Uniformity System, which corrects for critical-dimension non-uniformities on the incoming wafer. The company also unveiled an atomic layer etch (ALE) capability on the 2300 Kiyo F Series conductor etch system, which is paired with Lam’s atomic layer deposition (ALD) systems, the VECTOR ALD Oxide system for dielectric film ALD and the ALTUS system for tungsten metal film ALD.

Applied Materials and Tokyo Electron set plans in 2013 to merge their companies. The merged company, to be called Eteris, would have commanded about one-third of the worldwide etching equipment market. The merger was called off in April, however, as U.S. antitrust regulators indicated that they would not approve the transaction.

SEMI cheered a decision by the U.S. Department of Commerce in February to remove export controls on certain etch equipment, concluding a four-month investigation. SEMI had petitioned the federal government agency in July 2014 to look at the foreign availability of anisotropic plasma dry etching equipment.

“SEMI stands for free trade and open markets to support the development and success of the global semiconductor manufacturing industry supply chain,” Denny McGuirk, president and CEO of SEMI, said in a statement. “We applaud the decontrol of semiconductor etch equipment as a rational response to current technology, trade, and commercial realities. This is a win for both equipment makers and their customers operating in the global market.”

“The Commerce Department’s decision to remove export control restrictions for etch equipment is a big victory for the U.S. semiconductor equipment sector and our customers around the world,” said Randhir Thakur, executive vice president and general manager of the Silicon Systems Group at Applied Materials. “Recognizing the availability of these tools will help fuel growth and promote the success of the global industry supply chain.”

In May, imec and Tokyo Electron presented a direct copper etch scheme for patterning copper interconnections. This would replace the usual copper damascene process, according to imec and TEL. The Belgian research organization worked with nine leading chipmakers on developing the direct copper etch technology.

Dry or wet, etching technology will be the subject of discussions at the SEMICON West 2015 conference and exhibition.

By Jeff Dorsch, Contributing Editor

There are four main segments in the thin-layer deposition equipment market – atomic layer deposition, chemical vapor deposition, epitaxy, and physical vapor deposition, also known as sputtering.

As the semiconductor industry powers through the 14-nanometer process generation, interest is keen on how researchers and suppliers will improve the current crop of deposition equipment to meet the requirements of the 10nm and 7 nm nodes.

The long-pending merger of Applied Materials and Tokyo Electron into a company to be called Eteris, called off in April due to regulatory issues, would have created a mighty deposition vendor, holding nearly 60% of the worldwide market. Applied still holds a commanding share of the deposition market, yet will have to contend with Lam Research (which acquired Novellus Systems in 2012), AIXTRON, ASM International, and other competitors.

Global Industry Analysts (GIA) forecasts the global deposition equipment market will hit $13.6 billion by 2020. Atomic layer deposition (ALD) will be the fastest growing segment, with a compound annual growth rate of 19.9 percent, the market research firm estimates.

Chemical vapor deposition (CVD) will be the second largest deposition segment through the end of this decade, followed by physical vapor deposition (PVD) and epitaxy, according to GIA. Japanese vendors, namely Hitachi Kokusai Electric/Kokusai Semiconductor Equipment and Tokyo Electron, dominate the worldwide CVD market, with significant market shares held by Applied Materials, ASM International, and Lam Research, the market research firm states.

Taiwan is the world’s largest market for deposition equipment, Global Industry Analysts says. That’s not surprising, since SEMI estimates that Taiwanese semiconductor manufacturers will spend about $10.5 billion on wafer fabrication equipment this year, representing nearly 30 percent of worldwide spending on fab equipment in 2015. GIA sees China being among the fastest-growing markets for deposition, with a CAGR of 15.1 percent.

In May, Applied Materials introduced the Applied Endura Cirrus HTX PVD system for making titanium nitride hardmask films, targeting applications in fabricating semiconductors with 10nm and 7nm features.

A year ago at SEMICON West, the company debuted the Applied Producer XP Precision CVD system, which it said supports the industry transition to 3D NAND flash memory devices by providing nanometer-level layer-to-layer film thickness control for critical-dimension uniformity across a wafer.

July of 2014 also saw Lam Research unveil its VECTOR ALD Oxide system to produce conformal dielectric films defining critical pattern dimensions in multiple patterning.

SEMICON West 2015 is expected to see announcements on new products and research in the deposition equipment field.

By Jeff Dorsch

Chemical mechanical planarization (CMP) technology has been around for a long time. In addition to the semiconductor industry, CMP has applications in data storage, polishing the rigid disks and magnetic heads of hard-disk drives.

Those interested in learning about developments in CMP for hard drives and integrated circuits would do well to attend the CMP Technical and Market Trends session on Thursday, July 16, at 11 a.m. in the TechXPOT North area of Moscone Center’s North Hall. Representatives of Intel, HGST, Entegris, TDK, and other companies will be speaking.

While 450-millimeter wafers haven’t been much in the news this year, Thursday’s session will include a presentation by the Global 450 Consortium, with speakers from the College of Nanoscale Science + Engineering (CNSE) and SEMATECH.

CNSE is part of the SUNY Polytechnic Institute in Albany, N.Y., which also contains the Chemical Mechanical Planarization Center, a joint program with SEMATECH. Mitsubishi Chemical joined the program this spring.

While CMP is still used for its traditional polishing applications for interlayer dielectrics, it’s also finding employment in more advanced applications, such as bulk oxide polishing, shallow trench isolation, “stop on poly” isolation, and polishing of various dielectrics in advanced transistor designs.

CMP includes consumable products, polishing pads and slurries. Dow Chemical is the leading vendor in polishing pads, while Cabot Microelectronics dominates the CMP slurry market.

Late last month, Applied Materials and Cadence Design Systems announced that they are collaborating on optimizing the CMP process through silicon characterization and modeling for ICs with 14-nanometer features, and beyond that process node. Cadence, one of the leading vendors of electronic design automation software and services, will provide its CMP Predictor and CMP Process Optimizer tools. Applied will employ its Reflexion LK Prime CMP system.

“From our collaboration, we expect to more accurately predict gate height, dishing and erosion on each step of the CMP process, which could enable design and manufacturing teams to achieve higher yield and deliver advanced-node designs to market faster,” Derek Witty, vice president and general manager of Applied’s CMP Products Group, said in a statement.

Whatever your level of expertise in CMP, SEMICON West 2015 will help you polish up your knowledge of the field.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the HERCULES NIL—a fully integrated track system that combines cleaning, resist coating and baking pre-processing steps with EVG’s SmartNIL large-area nanoimprint lithography (NIL) process in a single platform. Offering industry-leading productivity and throughput, the HERCULES NIL provides a complete, dedicated UV-NIL solution that is ideally suited for high-volume manufacturing (HVM) of emerging photonic devices. It does so by imprinting structures in sizes ranging from tens of nanometers up to several micrometers that alter or improve the optical response of surfaces and devices, such as anti-reflective layers, color and polarizer filters, light guiding plates, patterned sapphire substrates used in manufacturing light emitting diodes (LEDs), and many others. Other rapidly emerging applications for NIL include MEMS, NEMS, biological and nano-electronic applications.

“The HERCULES NIL demonstrates EVG’s ‘Triple i’ philosophy of ‘invent-innovate-implement’ at work,” stated Paul Lindner, executive technology director at EV Group. “EVG has been an early pioneer in the development of NIL equipment. After more than a decade of research and continuous improvements, EVG has now propelled NIL technology to a level of maturity that enables significant advantages for certain applications compared to traditional optical lithography. In addition, the Hercules NIL allows a wider array of applications, particularly in the fields of photonics and biotechnology, to finally leverage the cost-of-ownership and resolution benefits of NIL in volume production.”

The HERCULES NIL combines EVG’s expertise in NIL, resist processing and HVM solutions into a single integrated system that offers unmatched throughput (40 wph for 200-mm wafers). The system is built on a highly configurable and modular platform that accommodates a variety of imprint materials and structure sizes—giving customers greater flexibility in addressing their manufacturing needs. The fully integrated approach also minimizes the risk of particle contamination.

Key product attributes include:

  • Fully automated UV-NIL imprinting and low-force detachment
  • Processing substrates up to 200mm in diameter
  • Full-area imprint coverage, which avoids pattern stitching errors associated with step-and-repeat lithography systems due to limited field size
  • Volume manufacturing of structures down to 40nm and smaller
  • Highest coating uniformity of +/- 1 percent, which results in minimal residual layer thickness and variation for processed structures over the entire wafer
  • Supports a wide range of structure sizes and shapes, including 3-D
  • Can be used on high-topography (rough) surfaces
  • Ability to fabricate multiple-use soft stamps to extend the lifetime of master imprint templates

EVG’s new HERCULES NIL system is available now. Systems have already been installed and are being used for high-volume manufacturing at production sites of leading photonic device manufacturers.

Digital Specialty Chemicals Limited (DSC), a dual bottom line corporation and leading provider of advanced materials to the semiconductor, pharmaceutical, and specialty chemical markets, announced that it has received an equity investment from Intel Capital, Intel Corporation’s global investment organization. The investment will enhance the company’s research and development capabilities and will accelerate manufacturing capacity expansion.

DSC specializes in the manufacture of organophosphorus and organometallic chemistries used in both memory and logic thin film atomic layer deposition (ALD) manufacturing processes at leading semiconductor integrated circuit (IC) fabrication sites worldwide. The company is a leader in the manufacturing and handling of both novel specialty chemicals in large volume, high purity air- sensitive chemicals that require nitrogen and vacuum-operated vessels, using high pressure reactors and multiple distillation techniques.

“Since 1987, we have provided custom and high volume high purity chemicals to the semiconductor, pharmaceutical and specialty chemical markets worldwide. Our people, processes and facilities combine to offer the agility of a small, fine- chemical operation with the capacity of a large supplier,” said Dr. Ravi R. Gukathasan, CEO. “We believe that the continuation of Moore’s Law for semiconductor processing will depend greatly on continued innovation of advanced precursors which provides a growth opportunity for DSC. The funding from Intel Capital will help enable us to construct R&D and manufacturing facilities to meet growing demand for thin film technologies.”

“Materials innovation is critical to enabling new capabilities in semiconductor device design and manufacturing,” said Robert Bruck, corporate vice president and general manager of Global Supply Management at Intel. “We look forward to supporting DSC’s growth including development of new materials technologies for advanced semiconductor manufacturing process technology nodes.”