Category Archives: Resource Guide

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 26,000 professionals from the electronics manufacturing supply chain attend SEMICON West and the co-located Intersolar. The “Best of West” award was established to recognize new products moving the industry forward with technological developments in the electronics supply chain.

Selected from over 600 exhibitors, SEMI announced today that the following Best of West 2017 Finalists will be displaying their products on the show floor at Moscone Center from July 11-13:

  • Mentor, a Siemens Business: Tessent® Cell-Aware Diagnosis – With FinFETs in high volume, finding systematic yield issues at the transistor level is important. The Tessent Cell-Aware Diagnosis technology significantly improves diagnosis of defects beyond the inter-connect and inside the logic cells. (Process Control, Metrology and Test Category; North Hall Booth #6661)
  • Microtronic Inc.: EAGLEview 5 Macro Defect Management Platform – EagleView 5 is the new, yield-enhancing, breakthrough macro defect inspection platform that was developed – and deployed in production — through collaboration with several leading device manufacturers who wanted to standardize and unify wafer defect management throughout their fab. Innovations include: dramatically improved defect detection; level-specific sorting; and integration with manual microscopes. (Process Control, Metrology and Test Category; North Hall Booth #5467)
  • SPTS Technologies Ltd: SentinelTM End-Point Detection System for Plasma Dicing after Grind – The Sentinel™ End-Point Detection System improves the control of plasma dicing processes and protects taped wafers for improved yields.  In addition to signaling exposure of the tape, Sentinel™ also detects loss of active cooling during the process to enable intervention to prevent yield loss. (Process Control, Metrology and Test Category; West Hall Booth #7617)
  • TEL: Stratus P500 – The Stratus P500 system electroplates panel substrates with wafer level processing precision.  As redistribution layers (RDL) reduce to widths below 10 µm line/space, and package sizes increase, conventional plating systems are challenged to meet system-on-package requirements. The P500 makes panel scale fine line RDL and feature filling applications possible. (Assembly/Packaging Solutions Category; North Hall Booth #6168)

Congratulations to each of the Finalists. The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 12, 2017.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced it is demonstrating optimized pre-processing solutions for the implementation of plasma dicing for advanced semiconductor packaging applications. EVG’s latest products and process development services support this emerging semiconductor back-end fabrication process by protecting bumps and other topography with highly uniform resist layer and lithographic patterning of narrow dicing streets. By combining EVG’s systems with third-party dry plasma dicing systems, customers can obtain a complete solution that will enable highly parallel, high-throughput, debris-free die singulation without risking bump reliability or impacting structured surfaces. EVG’s offerings address the critical pre-processing requirements for mid-end-of-line (MEOL) and back-end-of-line (BEOL) processing of MEMS, power devices, RFID components, image sensors, logic and memory.

Thinner and smaller semiconductor chips are required to support the latest generation of mobile and wearable devices as well as to facilitate the Internet of Things (IoT). Plasma dicing offers numerous advantages for die singulation, such as reducing dicing street widths, providing flexible chip layouts as well as eliminating sidewall damage, chipping and wafer breakage. However, plasma dicing also brings new pre-process requirements, including the need for protecting top-side or bottom-side structures prior to singulation, conformal coating of severe topography features, thick resists for deep etching, and lithography to open up the dicing lanes.

EVG’s high-quality, low cost-of-ownership resist processing and lithography systems address all of the pre-processing steps needed for advanced plasma dicing, including resist coating and development, as well as mask alignment lithography:

  • EVG’s proprietary OmniSpray technology enables uniform coating of high-topography surfaces and bumps across the wafer—where traditional spin-coating techniques are limited—with sufficient thickness to fully protect bumps during plasma processing while providing the base for lithographic patterning of dicing streets.
  • EVG’s mask aligners provide optimal patterning quality with spray coating resists, including excellent depth of focus, high uniformity over topography, high throughput, and high resolution in deep cavities and trenches (down to 10µm even for large proximity gaps wider than 100µm), making them ideally suited to expose and open up the dicing lines.
  • The pre-processing line is completed with EVG’s high-throughput development systems.
  • All systems can be provided in semi-automated and fully automated configurations, and are fully compatible with film-frame handling, making them ideally suited for die singulation in advanced packaging.

“The semiconductor industry is increasingly driving device performance through vertical stacking on thinner substrates. This trend is leading to greater demand not only for new wafer dicing technologies, but also for the supporting pre-processing equipment such as our coat, develop and mask alignment systems,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “We are pleased to offer demonstrations of our complete line of R&D and volume-production pre-processing systems for plasma dicing at our demo labs in Austria, the U.S. and Japan, where customers can witness the yield and cost-of-ownership benefits of this powerful end-to-end wafer dicing solution for their custom advanced packaging needs.”

EVG will also showcase its latest suite of lithography and resist processing solutions for advanced packaging applications at SEMICON West, to be held July 11-13 at the Moscone Convention Center in San Francisco, Calif. Attendees interested in learning more can visit EVG at Booth #7211 in the West Hall.

Researchers from MIPT’s Center of Shared Research Facilities have found a way to control oxygen concentration in tantalum oxide films produced by atomic layer deposition. These thin films could be the basis for creating new forms of nonvolatile memory. The paper was published in the journal ACS Applied Materials & Interfaces, which has an impact factor of 7.14.

Want nonvolatile memory that’s fast as RAM and has the capacity of flash?

Because data storage and processing solutions are so central to modern technology, many research teams and companies are pursuing new types of computer memory. One of their major goals is to develop universal memory — a storage medium that would combine the high speed of RAM with nonvolatility of a flash drive.

A promising technology for creating such a device is resistive switching memory, or ReRAM. It works by changing the resistance across a memory cell as a result of applied voltage. Since each cell has a high- and a low-resistance state, it can be used to store information, e.g., in the form of zeros and ones.

A ReRAM cell can be realized as a metal-dielectric-metal structure. Oxides of transition metals such as hafnium and tantalum have proved useful as the dielectric component of this layered structure. Applying voltage to a memory cell that is based on these materials causes oxygen migration, changing its resistance. This makes the distribution of oxygen concentration in the oxide film a crucial parameter determining the functional properties of the memory cell.

However, despite significant advances in ReRAM development, flash memory shows no sign of losing ground. The reason for this is that flash memory allows for three-dimensional memory cell stacking, which enables a much greater storage density. In contrast to this, oxygen-deficient film deposition techniques normally used in ReRAM design are not applicable to functional 3-D architectures.

That’s where atomic layer deposition comes in

In a bid to find an alternative technique, MIPT researchers turned to atomic layer deposition, a chemical process by which thin films can be produced on the surface of a material. During the last decade, ALD has become increasingly widespread, with numerous applications in nanoelectronics, optics, and the biomedical industry. There are two major advantages to atomic layer deposition. The first one is the unprecedented control over film thickness: It is possible to deposit films that are several nanometers thick with an error of a fraction of a nanometer. The other advantage is that ALD enables conformal coating of 3-D structures, which is problematic for most of the currently used nanofilm deposition techniques.

In an ALD process, a substrate is sequentially exposed to two chemicals that are known as the precursor and the reactant. It is the chemical reaction between these two substances that produces a coating layer. In addition to the element used in the coating, precursors contain other compounds — e.g., of carbon or chlorine — called ligands. They facilitate the reaction but, in an ideal ALD process, have to be completely removed from the resulting film once the interaction with the other chemical (reactant) has occurred. It is vital to choose the right substances for use in atomic layer deposition. Although it proves difficult to deposit oxide films with variable oxygen concentration by ALD, they are essential for ReRAM.

“The hardest part in depositing oxygen-deficient films was finding the right reactants that would make it possible to both eliminate the ligands contained in the metallic precursor and control oxygen content in the resulting coating,” says Andrey Markeev, who holds a PhD in physics and mathematics and is a leading researcher at MIPT. “We achieved this by using a tantalum precursor, which by itself contains oxygen, and a reactant in the form of plasma-activated hydrogen.” Confirming the experimental findings turned out to be a challenge in itself. As soon as the experimental sample is removed from the vacuum chamber, which houses it during ALD, and exposed to the atmosphere, this causes modifications in the top layer of the dielectric, making it impossible to detect oxygen deficiency using analytic techniques such as electron spectroscopy, which target the surface of the sample.

“In this study, we needed not just to obtain the films containing different amounts of oxygen but also to confirm this experimentally,” says Konstantin Egorov, a PhD student at MIPT. “To do this, our team worked with a unique experimental cluster, which allowed us to grow films and study them without breaking the vacuum.”

By Paula Doe, SEMI

Fabs and tool makers are starting to pay a lot more attention to suppliers of components and subsystems– as defects in these materials start to impact yields at 14nm and below. Solving these emerging issues, though, will take a collaborative effort to determine what parameters matter, how to measure them, and how to trace them back across an extended supply chain, suggests Pawitter Mangat, GLOBALFOUNDRIES director of Global Incoming Quality, one of the speakers who’ll discuss these issues in the program on component impact on yields at advanced nodes, July 11, at SEMICON West 2017.

“As we move below 22nm, even the composition of the materials in the subcomponents become critical,” he says. “But currently there is no general agreement on what the important parameters are to control for particular applications, or on how to measure these parameters with the same methods for consistent results.” The issues are often with the industrial grade raw materials from which the subcomponents are made, and these industrial chemical suppliers may be reluctant to invest in controls as the semiconductor industry represents only a tiny percentage of their business. “This means we need to look beyond our immediate suppliers to a wider ecosystem of components and material suppliers, and to extend digital traceability through this wider ecosystem as well,” he notes. “If we have an issue, we need to be able to quickly trace it back to the cause.”

“The 7nm world tends to forget that all subcomponents, everything, has been developed for other industries, not the semiconductor industry, and the makers of all these basic pumps and valves and O-rings have no way of knowing what the important parameters are to prevent defects in the final semiconductor devices,” notes Dalia Vernikovsky, CEO, Applied Seals North America, and co-chair of the SEMI Semiconductor Components, Instruments, and SubSystems (SCIS) special interest group.

She suggests the major users and suppliers get together to come up with the basic parameters for things like metal contamination, surface cleanliness or outgassing for specific components for specific processes, and then agree on a common way to measure these parameters, to enable tracing and characterizing the defects in the final devices.   This is also the first step towards specifying and controlling the parameters of the raw materials used in the components and subsystems that also matter. “If I am going to push my supplier, I have to be able to show him what the end customers’ requirement is,” notes Vernikovsky.  “This is not about individual companies’ intellectual property. It’s the basic requirement of the IC industry that we all need to meet, and then we can compete on a higher level.”

Other speakers at the Semiconductor Components, Instruments and Subsystems (SCIS) session include Norm Armour, Micron Technology, Managing Director Worldwide Facilities and Corporate EHSS; Sanchali Bhattaharjee, Intel, Engineering Manager, Global Supply Chain Management; and a panel with the speakers moderated by Dan Hutcheson, VLSI Research, CEO and Chairman. The SEMI SCIS special interest group will also have an open meeting on their current collaborative efforts July 13 at the Marriott Marquis. See www.semiconwest.org/programs-catalog/enabling-hvm-advanced-process-nodes.

Worldwide semiconductor wafer-level manufacturing equipment (WFE) revenue totaled $37.4 billion in 2016, an 11.3 percent increase from 2015, according to final results by Gartner, Inc. The top 10 vendors accounted for 79 percent of the market, up 2 percent from 2015.

“Spending on 3D NAND and leading-edge logic process drove growth in the market in 2016,” said Takashi Ogawa, research vice president at Gartner. “This spending was driven by momentum for high-end services in data centers and requirements for faster processors and high-volume memory for mobile devices.”

Applied Materials continued to lead the WFE market with 20.5 percent growth in 2016 (see Table 1). The active investment in 3D device manufacturing provided significant momentum in Applied’s etch revenue, specifically in the conductor etch segment. Screen Semiconductor Solutions experienced the highest growth in the market, with 41.5 percent. This was due to a combination of the appreciation of the Japanese Yen against the U.S. dollar, which elevated dollar-based sales estimates and the demand in premium smartphone and data center servers for big data analysis that drove investment in 3D-NAND capacity and leading-edge technology in foundries.

Table 1

Top 10 Companies’ Revenue From Shipments of Total Wafer-Level Manufacturing Equipment, Worldwide (Millions of U.S. Dollars)

Rank 2015

Rank 2014

Vendor

2016 Revenue

2016 Market Share (%)

2015

Revenue

2015 Market Share (%)

2015-2016 Growth (%)

1

1

Applied Materials

7,736.9

20.7

6,420.2

19.1

20.5

2

4

Lam Research

5,213.0

13.9

4,808.3

14.3

8.4

3

2

ASML

5,090.6

13.6

4,730.9

14.1

7.6

4

3

Tokyo Electron

4,861.0

13.0

4,325.0

12.9

12.4

5

5

KLA-Tencor

2,406.0

6.4

2,043.2

6.1

17.8

6

6

Screen Semiconductor Solutions

1,374.9

3.7

971.5

2.9

41.5

7

7

Hitachi High-Technologies

980.2

2.6

788.3

2.3

24.3

8

8

Nikon

731.5

2.0

724.2

2.2

1.0

9

9

Hitachi Kokusai

528.4

1.4

633.8

1.9

-16.6

10

13

ASM International

496.9

1.3

582.5

1.7

-14.7

Others

7,988.0

21.4

7,586.2

22.6

5.3

Total Market

37,407.3

100.0

33,613.7

100

11.3

Source: Gartner (April 2017)

Additional information is provided in the Gartner report “MarketShare: SemiconductorWaferFab Equipment, Worldwide, 2016.” The report provides rankings and market share for the top 10 vendors. In 2015, Gartner changed the segment reporting to focus on wafer-level manufacturing and is no longer providing segment details for die-level packaging or automatic test. This report is limited to wafer-level manufacturing equipment.

3D-Micromac AG, a developer of laser micromachining and roll-to-roll laser systems for the photovoltaic, medical device and electronics markets, today announced that the total received order volume for its microCELL TLS high-throughput half-cell cutting tools tops 1.5 GW for tool deliveries in 2017 to date.

The microCELL TLS systems use Thermal Laser Separation for cleaving solar cells into half-cells. This process provides a multitude of mechanical and electrical benefits to customers. The separated cells show a significantly higher mechanical strength, better edge quality as well as lower power reduction compared to laser scribing and cleaving approaches. A module power gain of more than 1 W was seen with TLS compared to conventional scribe and break methods, in addition to the 5-7 W per module gain of half-cell module technology.

Further cementing its position as the market leader for laser systems in photovoltaics,
3D-Micromac also yesterday introduced its second-generation microCELL OTF system, the high-performance production solution for Laser Contact Opening (LCO) of Passivated Emitter Rear Contact (PERC) solar cells, which achieves a world-class throughput of 8,000 wafers per hour.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today unveiled the IQ Aligner NT–its latest and most advanced automated mask alignment system for high-volume advanced packaging applications. Featuring high-intensity and high-uniformity exposure optics, new wafer handling hardware, full 200-mm and 300-mm wafer coverage that enables global multi-point alignment, and optimized tool software, the new IQ Aligner NT provides a 2X increase in throughput and 2X improvement in alignment accuracy over EVG’s previous-generation IQ Aligner. The system surpasses the most demanding requirements for wafer bump and other back-end lithography applications while providing up to 30 percent lower cost of ownership compared to competing systems.

The IQ Aligner NT from EV Group is the industry's most advanced automated mask alignment system for advanced packaging applications. It provides a 2X increase in throughput and 2X improvement in alignment accuracy over the previous-generation system, as well as up to 30 percent lower cost of ownership compared to competing systems.

The IQ Aligner NT from EV Group is the industry’s most advanced automated mask alignment system for advanced packaging applications. It provides a 2X increase in throughput and 2X improvement in alignment accuracy over the previous-generation system, as well as up to 30 percent lower cost of ownership compared to competing systems.

The IQ Aligner NT is ideally suited for a variety of advanced packaging types, including Wafer-level Chip Scale Packaging (WLCSP), Fan-out Wafer Level Packaging (FOWLP), 3D-IC/Through-silicon Via (TSV), 2.5D Interposers, and Flip Chip.

New lithography capabilities needed

Semiconductor advanced packaging is continually evolving to enable new types of devices with increasing functionality at a lower cost per function. As a result, new developments in lithography are now required to address the unique needs of the advanced packaging market. These needs include:
Extremely tight alignment accuracy
Managing wafer warpage and addressing dimensional mismatch of wafer and mask layout to achieve optimized overlay

Sufficient exposure of the thicker resists and dielectric layers found in back-end processing
Higher resolution to address shrinking bumps and interconnects due to device scaling
At the same time, all of these needs must be met in a highly cost-effective and high-productivity lithography tool platform.

“Leveraging more than three decades of experience in lithography, EVG has pushed the envelope of mask alignment technology to new boundaries with our new IQ Aligner NT,” stated Paul Lindner, executive technology director at EV Group. “This latest addition to our suite of lithography solutions provides unprecedented levels of throughput, accuracy and cost-of-ownership performance, which in turn has opened up a variety of new market opportunities for EVG. We look forward to working closely with customers to meet their critical advanced packaging lithography needs.”

The IQ Aligner NT incorporates a variety of improvements to achieve industry-leading mask alignment performance for advanced packaging lithography:

High-power optics provides a 3X increase in illumination intensity compared to EVG’s previous-generation IQ Aligner, making it ideal for exposing thick resists and other films associated with processing bumps, pillars and other high-topography features:

  • Full clearfield mask movement over 300-mm substrates, which offers the highest process compatibility and flexibility in dark field mask alignment and pattern positioning
  • Dual substrate size concept eliminates the need for any retooling effort, providing a quick and easy on-the-fly bridge tool for two different wafer sizes
  • Fully automated as well as semi-automated/manual wafer loading operation is supported for maximum flexibility
  • Latest EVG CIMFramework system software based on the latest fab software standards and protocols
  • Unsurpassed accuracy and productivity performance

Combining optical and mechanical engineering with optimized tool software, the IQ Aligner NT provides a two-fold increase in throughput (>200 wph for first print, >160 wph for top side alignment) as well as a two-fold improvement in alignment accuracy (250nm 3-sigma). As a result of the tighter alignment specification, customers can also realize improved yields for high-end and high-bandwidth packaging products.

Today, SEMI announced updates to its World Fab Forecast report, revealing that fab equipment spending is expected to reach an industry all-time record − more than US$46 billion in 2017.  The record is expected to be broken again in 2018, nearing the $50 billion mark. These record-busting years are part of three consecutive years of growth (2016, 2017 and 2018), which has not occurred since the mid-1990s. The report has been the industry’s most trusted data source for 24 years, observing and analyzing spending, capacity, and technology changes for all front-end facilities worldwide. See Figure 1.

fab equipment spending

Figure 1: Fab Equipment Spending (Front End Facilities)

SEMI‘s World Fab Forecast report (end of February 2017) provides updates to 282 facilities and lines equipping in 2017, 11 of which are expected to spend over $1 billion each in 2017. In 2018, SEMI’s data reflect 270 fabs to equip, with 12 facilities spending over $1 billion each.  The spending is mainly directed towards memory (3D NAND and DRAM), Foundry and MPU.  Other strong product segments are Discretes (with LED and Power), Logic, MEMS (with MEMS/RF), and Analog/Mixed Signal.

SEMI (www.semi.org) forecasts that China will be third for regional spending in 2017, although China’s annual growth is minimal in 2017 (about 1 percent), as many of the new fab projects are in the construction phase.  China is busy constructing 14 new fabs in 2017 and these new fabs will be equipping in 2018. China’s annual spending growth rate in 2018 will be over 55 percent (more than $10 billion), and ranking in second place for worldwide spending in 2018.  In total for 2017, China is equipping 48 fabs, with equipment spending of $6.7 billion; looking ahead to 2018, SEMI predicts that 49 fabs to be equipped, with spending of about $10 billion.

Other regions also show solid growth rates.  The SEMI World Fab Forecast indicates that Europe/Mideast and Korea are expected to make the largest leaps in terms of growth rates this year with 47 percent growth and 45 percent growth, respectively, year-over-year (YoY).  Japan will increase spending by 28 percent, followed by the Americas with 21 percent YoY growth.

The SEMI Industry Research & Statistics team has made 195 changes on 184 facilities/lines in the last quarter, with eight new facilities added and three fab projects cancelled. SEMI’s World Fab Forecast provides detailed information about each of these fab projects, such as milestone dates, spending, technology node, products, and capacity information. The World Fab Forecast Report, in Excel format, tracks spending and capacities for over 1,100 facilities including future facilities across industry segments.  The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, in-house equipment, and spending on facilities for equipment. Also check out the Opto/LED Fab Forecast.

ULVAC Technologies, Inc. (www.ulvac.com), a supplier of production systems, instrumentation and vacuum pumps for technology industries, has been selected by a global MEMS inertial sensor manufacturer to deliver an ULVAC ENVIRO-1Xa advanced plasma ashing system for running critical low-temp descum processes and high-temp bulk photoresist strip processes. These steps are crucial for the manufacturing of high-performance accelerometers and gyroscopes used in consumer, automotive, health and fitness, and industrial applications.

The ENVIRO-1Xa is the latest photoresist removal equipment from ULVAC, and offers superior performance at an exceptional price. The system is equipped with a versatile platform that can handle multiple wafer sizes, ranging from 4-inch to 8-inch in diameter. The system is capable of high-speed photoresist removal at more than 10µm/min, but has the process flexibility required for other important operations, such as; high-dose implanted resist removal, descum and surface modification, SU-8 and fluorinated resist removal, and MEMS sacrificial-layer removal.

Wayne Anderson President/CEO of ULVAC Technologies, Inc. states that “The sale of this ENVIRO 1Xa, for descum applications, serves to increase our market penetration in the global MEMS manufacturing marketplace, where we have been very successful with our MEMS product portfolio; which includes plasma etching equipment, sputter deposition equipment and the ENVIRO family of plasma ashing equipment.”

ClassOne Technology (www.classone.com), manufacturer of cost-efficient wet processing equipment for ≤200mm substrates, announced a new company-wide initiative to reduce costs of operation (CoO) in copper plating processes.

“From the beginning, our mission has been to bring more advanced and lower priced plating capabilities to all the emerging markets who work with smaller wafers,” said ClassOne Technology President, Kevin Witt. “Our Solstice systems are already the industry’s most affordable tools for ≤200mm plating. Now we want to enable economies on the cost of ownership side, as well — perhaps reducing those expenses by as much as 25 to 30%. And that’s our goal in this initiative.”

The company explained that it sees potential for shrinking Cu plating CoO by reducing chemical consumption, extending the life of consumables and equipment parts, increasing and optimizing throughput, and enhancing chamber performance, among other areas. Company representatives stated that they are working toward innovative ways to increase efficiencies, minimize waste, streamline operation and optimize performance in each of the copper plating processes.

“Copper plating is an extremely hot area of interest right now in a great many emerging markets,” said Witt. “That’s why ClassOne focuses serious attention on it. We want to continue to be the go-to guys for absolutely everything having to do with copper plating on smaller wafers.”

“And that’s why you’ll be seeing more new copper-related announcements coming from ClassOne in the coming weeks and months,” he added.

ClassOne Technology offers a selection of new wet processing tools specifically designed for users of 75mm to 200mm wafers. These include three different models of Solstice electroplating systems for production and development as well as the Trident families of Spin-Rinse-Dryers and Spray Solvent Tools. All are priced at less than half of what similarly configured systems from the larger manufacturers would cost — which is why the ClassOne lines are often described as delivering “Advanced Wet Processing for the Rest of Us.”