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Stanford University researchers sponsored by Semiconductor Research Corporation (SRC) have developed a new area selective atomic layer deposition (ALD) process that promises to accelerate the manufacturing of higher performing, more energy efficient semiconductors.

It is well known that next-generation electronic, optoelectronic and sensing devices that contain nanoscale dimensions face increasingly difficult materials and fabrication challenges as the downward scaling of these devices continues. Conventional semiconductor manufacturing processes are time-consuming and expensive, in part due to the need for lithographic patterning. The Stanford research leverages simple ALD and etching processes that eliminate this lithography step and improve selective deposition of dielectric materials by more than 10 times in film thickness compared to similar advanced processes.

Due to difficulties of current top-down fabrication processes that contain multiple deposition, lithography and etching steps, along with problems with misalignment in lithography, using an alternative approach in which the desired materials are directly and selectively deposited would significantly facilitate the process, according to the Stanford team.

“Our technology is a promising candidate for overcoming the challenges of top-down processing and misalignment because it greatly improves the ability to perform selective deposition of materials. This research introduces a novel processing method to meet the increasingly difficult materials challenges associated with new devices,” said Dr. Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.

Current approaches utilize lithography for nanoscale patterning. Using lithography and etching for fabrication of 2D or 3D structures often results in misaligned features and causes a risk of shorting or high resistant areas. However, selective deposition using ALD can reduce these risks and reduce the process time and steps.

Bent explained that selective deposition allows layers of material to be added onto a substrate only where desired without the need for additional lithography steps. However, the high level of selectivity needed for a manufacture-worthy process has not yet been achieved in area selective deposition studies. In addition, most methods for area selective deposition require long processing times.

The Stanford research has been focused on selective deposition of dielectric materials on metal/dielectric patterns. These type of structures can be found in interconnects and back-end-of-line (BEOL) processing. With ALD being used in other stages of the device fabrication process as well, the results from the Stanford experiments can potentially be applied to a variety of nanoscale electronic, optoelectronic and sensing devices.

The research developments occurred during the second year of research on the topic, and the Stanford team is continuing to explore new methods for area selective ALD to improve both selectivity and manufacturability.

“The Stanford team’s research has shown for the first time that, by following selective deposition of a dielectric material using pre-treatment by an inhibitory material, they can significantly reduce the process time (from 48 hours to less than 1 hour) and also improve the limits of selective deposition of dielectrics by more than 10 times,” said Kwok Ng, Senior Science Director of Nanomanufacturing Materials and Processes at SRC.

AKHAN Semiconductor, Inc. (AKHAN SEMI), a developer of diamond semiconductor technology, this week announced that it is deploying 200mm manufacturing equipment and process in its new production facility in Gurnee, Illinois, continuing its preparation for delivering AKHAN diamond semiconductor based-technology products to the company’s first commercial customer this quarter.

“The proven, high-yielding 200mm semiconductor manufacturing process is proving ideal for the production of a wide range of semiconductors – sensors, MEMS, analog, power management – that are embedded in the rapidly growing number of connected devices, from smartphones and tablets to cars, home appliances, wearables, and commercial and industrial applications,” said AKHAN COO Carl Shurboff.

According to market research firm Gartner, Inc., the number of Internet-connected devices, now referred to as the Internet of Things, will grow from 6.3 billion in 2016 to more than 20 billion in 2020.

This explosion in connected products is driving high global demand for all types of new semiconductors to power this new era of connected computing. SEMI noted in its Global 200mm Fab Outlook to 2018 that 200mm fab capacity is expected to grow from 5.2 million wafer starts per month in 2015 to more than 5.4 million in 2018.

“The timing for our diamond-based semiconductor technology’s market debut could not be better,” said AKHAN CEO Adam Khan. “By using man-made diamonds at the core of our new chip technology, we are ushering in a new generation of semiconductor solutions that operate at higher temperatures, are thinner and require less power. These are exactly the attributes required for all the products that make up the Internet of Things.”

The AKHAN diamond semiconductor based technology will enable a new generation of commercial, industrial and consumer products such as flexible and transparent displays that can be used in wearables and thinner consumer devices that last longer. On the commercial side, AKHAN is already developing new diamond windows for industrial, defense and aerospace applications.

AKHAN’s technology is based on a new process that uses man-made diamond rather than silicon to produce new chip materials. It is a result of the marriage of two scientific breakthroughs: the ability to use nanocrystalline diamond (NCD) films and a new doping process the makes it possible to use NCD as a semiconductor material.

The new AKHAN production facility was opened in mid-November. The company is actively hiring to staff the new facility which is expected to employee 100 people in the next two years.

The Critical Materials Council for Semiconductor Fabricators, originally established by ISMI/SEMATECH in the early 1990’s, will be managed by TECHCET CA LLC starting January 01, 2016. Under its new name CMC Fabs, the membership-based organization of semiconductor fab & fabless manufacturers will continue working to identify and remediate issues impacting the supply, availability, and accessibility of both current and emerging semiconductor process materials. In keeping with SEMATECH tradition, the work of the international council takes place in a non-competitive environment for the benefit of the semi device fabrication community. Topics addressed are identified and prioritized by the member companies.

The organization has a new website at cmcfabs.org, which includes an overview of the Council’s mission, news of upcoming events and a Members Only portal for access to minutes of monthly phone/WebEx meetings and workshop details. The site also features access for Members to the TECHCET Critical Materials Reports and the related quarterly updates.

The next face-to-face meeting of CMC Fabs will take place May 3-6, 2016 in Hillsboro, Oregon. The meeting will include the annual CMC Materials Seminar held on May 5-6 that is open to the public. Sessions include a market briefing, supply chain issues and methods, the evolution of emerging materials in ALD / ALE, and the materials revolution around carbon. Speakers will be drawn from fabs, suppliers and analysts to address topics of concern and interest to the Council, and the semiconductor materials supply chain.

CMC Fabs is a unit of TECHCET CA LLC, a firm focused on Process Materials Supply Chains, Electronic Materials Technology, Materials Market Research and Consulting for the Semiconductor, Display, Solar/PV, and LED Industries. The company has been responsible for producing the SEMATECH Critical Material Reports since 2000.

Facilities


January 6, 2016

Semiconductor manufacturing facilities or wafer “fabs” are huge affairs costing billions of dollars. Most of the action takes place in the cleanroom which houses the manufacturing equipment, such as lithography, chemical vapor deposition, etch, ion implant, photoresist track systems, sputtering, annealing tools and many others. Large fabs have upward of 600 different tools, often multiple tools fo the same type to meet overall throughput targets (tens of thousands of wafers per month for large fabs).

In 2015, Samsung announced what is said to be the world’s most expensive semiconductor fabrication plant, at over $14 billion. The new plant will be finished in 2017, according to Samsung, and is reported to almost as big–at 31 million square feet plant–as Samsung’s next two biggest fabs put together at Giheung and Hwaseong South Korea. The new plant is reported to employ about 150,000 people and to produce about $40 billion dollars per year in chip revenue
Wafers are typically transported through the fab with an automated rail system (although hand transportation and loading is not uncommon). Most fabs transport the wafers in a FOUP (front opening unified pod), which is essentially an expensive plastic box.

Fabs require an intricate infrastructure to supply chemicals, materials and gases to the process tool. Air handlers, ionization systems and HEPA filters are used to clean the air in the cleanroom. Support equipment, such as vacuum pumps and gas abatement tools (used to remove process byproducts before the air is released into the atmosphere, for example) are typically housed in a sub-floor beneath the tools.

Fabs also require sophisticated MES (Manufacturing Execution Software) systems to keep track of the “recipes” for the process tools, track lots of wafers through the fab (and manage “hot” lots of wafers that need to be expedited) and keep track of materials.

Another concern is power. A typical wafer fab uses as much energy as 10,000 homes. Energy bills run as high as $25 million annually. New fabs use LEED principles to reduce costs.

Automated Test Equipment


January 6, 2016

Automatic or automated test equipment (ATE) is a system that performs tests on a device, known as the Device Under Test (DUT), using automation to quickly perform measurements and evaluate the test results. An ATE can be a simple computer controlled digital multimeter, or, more often, a complicated system containing dozens of complex test instruments (real or simulated electronic test equipment) capable of automatically testing and diagnosing faults in complex ICs.

The ATE/semiconductor test segment is comprised of six distinct types of testers:
• Analog/Linear Test
• Mixed Signal Test
• RF/Microwave Test
• Digital/Logic Test
• Memory Test
• System-on-Chip (SOC) Test

ATE systems interface with packaged chips through a separate machine called an IC handler. Tested ICs are then “binned” depending on their performance (higher performance devices are sold at a premium). Alternatively, ATE systems can test unpackaged chip directly on the wafer through a wafer prober and probe card designed to touch on the IO/bonding pads of the device. In this way, the cost of packaging bad chips is avoided.

The ATE market is driven by semiconductor chip volumes. As chip volumes steadily increase, the demand for chip testers also grows.

Given the sharp increase in usage of memory devices in end products such as home appliances, cell phones, and automobiles, it’s no surprise that the memory tester sub-segment is the largest in the ATE space.

According to a research report by Radiant Insights, Inc., the global ATE mrket is expected to be valued at $4.48 billion by 2020, as per Increasing design complexity coupled with need for effective testing is expected to drive the global automated test equipment market demand.

Increasing need for optimizing power management in order to ensure longer battery life is likely to favor the growth prospects. However, dependency on semiconductor chips is likely challenge industry participants. Non-memory products were the leading segment, valued at $2,867.5 million in 2013, according to the report. Expansion of consumer electronics, increasing automotive demand and growing number of microcontroller-based applications are factors likely to promote its demand.

Memory products accounted for 21.21% of the overall revenue in 2013, growing at an estimated CAGR of 1.7% from 2014 to 2020. The cyclical variations in growth rates than non-memory semiconductors have resulted in gaining popularity among various applications.

Additional Reading:

Business is good for vendors of test and inspection/metrology equipment

Lithography


January 6, 2016

The process of creating a pattern on a wafer is known as lithography. Typically, light is shone through a mask onto a photoresist that coats the wafer. After exposure, the photoresist is “developed,” which removes the exposed part of the resist (or the unexposed resist if it is negative resist). A photoresist coat/bake/develop system — often called a “track system” is typically connected directly to the wafer exposure tool or wafer “stepper.”

The exposed wafer is then etched, where the photoresist acts as a barrier to the etching chemicals or reaction ions. The photoresist is then removed by stripping or “ashing.” In complex integrated circuits, a modern CMOS wafer will go through the photolithographic cycle up to 50 times, making lithography one most critical process step.

Increasingly smaller wavelengths of light have been used to create smaller dimensions. Complex mask designs have also evolved, such as optical proximity correction (OPC), to correct for optical effects. Mask-source optimization techniques have also been developed to correct for variations in the source and on the wafer.

A push to extreme ultra-violet (EUV) lithography has been under way for a decade or more, led by ASML Lithography. Alternatives have also been research and developed, including nano-imprint lithography (NIL), which uses stencils and multi e-beam (MEB) lithography, which uses a large bank of individually controlled electron beams to expose the wafer directly (no mask required). More recently, an interesting approach called directed self-assembly (DSA) has been studied, which enables very small dimensions. DSA uses a guide structure on the wafer and polymer-based chemicals to create regular lines with very small dimensions.

Check out our Lithography Topic Center for regular updates.

Additional Reading:

Feed-forward overlay control in lithography processes using CGS

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

EUV lithography is on the threshold of becoming a mainstream patterning technology for sub-10nm chips, featured speaker Anthony Yen of Taiwan Semiconductor Manufacturing Co. (TSMC) will tell fellow attendees at SPIE Advanced Lithography 2016.

SPIE Litho will run February 21-25 in the San Jose (California) Marriott and Convention Center, and is sponsored by SPIE, the international society for optics and photonics.

In its 41st year in 2016, the annual event provides a focal point for the development of micro- and nanolithography and related technologies. It brings together participants from a wide range of sectors to share and learn about state-of-the-art lithographic tools, resists, metrology, materials, etch, design, and process integration.

Yen, a former SPIE Litho symposium chair and the director of TSMC’s Nanopatterning Technology Infrastructure Division, is one of three leading semiconductor lithography researchers scheduled to give plenary talks on Monday of the conference week.

Harry Levinson, GlobalFoundries Senior Director of Technology Research and Senior Fellow and another former SPIE Litho symposium chair, will review the evolution of lithographic technologies in his plenary talk, starting with the earliest simulation software through to EUV.

Richard Gottscho, Executive vice president of Global Products at Lam Research Corporation, will discuss how to minimize process-induced variability in multiple patterning.

SPIE Litho will offer more than 500 presentations in seven conferences, two poster receptions, 15 technical professional development courses, a two-day exhibition showcasing leading suppliers for the industry, and the first-ever SPIE Litho all-symposium welcome reception.

Mircea Dusa, Fellow and scientist at ASML US, Inc., is symposium chair, and Bruce Smith, Director of Microsystems Engineering at Rochester Institute of Technology, is cochair.

Among other highlights are:

  • the 30th anniversary celebration for the Metrology, Inspection, and Process Control conference with a “Wheel of Fortune” game
  • awarding of the 2016 SPIE Frits Zernike Award for Microlithography
  • a panel discussion on fundamental technology challenges in metrology, lithography, and design as critical dimensions for integrated circuits shrink to near-atomic scales.

Companies in the exhibition on Tuesday and Wednesday will include Canon USA, Inc., Carl Zeiss SMS GmbH, JSR Micro, Inc., Swiss Litho AG, Synopsys, Inc., Tokyo Electron Limited, Zygo Corporation, and others, both well-established industry leaders and newer companies.

Accepted conference proceedings papers will be published in the SPIE Digital Library as soon as approved after the meeting, and in print volumes and digital collections.

Registration, hotel, and other information is at www.SPIE.org/AL.

SPIE is the international society for optics and photonics, an educational not-for-profit organization founded in 1955 to advance light-based science and technology. The Society serves nearly 264,000 constituents from approximately 166 countries, offering conferences and their published proceedings, continuing education, books, journals, and the SPIE Digital Library in support of interdisciplinary information exchange, professional networking, and patent precedent. In 2015, SPIE provided more than $5.2 million in support of education and outreach programs. SPIE is a Founding Partner of the International Year of Light and Light-based Technologies and a Founding Sponsor of the U.S. National Photonics Initiative.

Rudolph Technologies, Inc., has received an order for over $15 million from an unnamed foundry in Asia for multiple NSX 330 Systems.

The systems will be used for inspection of next-generation fan-out wafer level packaging products, including whole-wafer inspection and post-saw inspection. The systems will begin shipping in the fourth quarter of 2015 with the majority shipping in the first quarter of 2016.

“We are pleased to partner with this industry leader to provide the market-leading NSX System for their next-generation packaging line,” said Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit. “Key factors of this win were the systems’ superior inspection sensitivity, capture rate, and throughput for two-dimensional (2D) inspection, while meeting the automation challenges inherent with fan-out wafers and film frames. Additionally, all systems will be equipped with Rudolph’s Discover Yield Management Software that enhances the user’s process analysis capability in real-time, enabling fast yield improvement and increasing the productivity of each tool and the overall fab yield. This level of process visibility is quickly becoming essential to factory efficiency.”

“Rudolph has been enabling its customers’ development of advanced packaging processes for nearly two decades. We are pleased that our experience, combined with our unique fusion of hardware and software solutions, was selected to help our customer quickly ramp and control such a critical project,” said Mike Plisinski, CEO of Rudolph. “The development of advanced packaging solutions is a priority for many of our customers, as more of their customers specify packages utilizing fan-out, panel, and copper pillar technology to reduce the cost of devices while improving performance.”

Plisinski adds, “While the 2016 forecast for the overall semiconductor industry remains relatively subdued at 1.9 percent growth, according to Gartner, the development of next-generation advanced packaging processes continues to be an important growth driver for Rudolph. We are pleased that our comprehensive solutions-process, process control, and software-are helping to enable this growth.”

ORBOTECH LTD. today announced that SPTS Technologies, an Orbotech company and a supplier of advanced wafer processing solutions for the global semiconductor and related industries, has supplied CEA-Leti, one of Europe’s largest micro- and nanotechnologies research institutes, with its vapor HF etch release systems for 300mm microelectromechanical systems (MEMS) on CMOS development. Installed in 2015 at CEA-Leti’s facility in Grenoble, France, the Monarch300 joins the 200 and 300mm etch, CVD and PVD systems previously supplied by SPTS and which are already operational in CEA-Leti’s MEMS and packaging lines.

“The co-integration of MEMS and CMOS has the potential to create a new family of sensors with improved performance,” said Kevin Crofton, President of SPTS and Corporate Vice President at Orbotech. “The Monarch 300 uses our patented Primaxx vapor HF etch technology and is capable of processing thirteen 300mm wafers simultaneously. NEMS and MEMS are at the core of CEA-Leti’s activities, and we are pleased to be able to supply this highly valued partner with additional capability to support its 300mm MEMS program.”

Marie-Noëlle Semeria, CEO of Leti and President of the Nanoelec RTI board, commented: “MEMS devices co-integrated with CMOS help Leti achieve a long-standing goal of enabling smaller and more powerful sensors and actuators, without exceeding power budgets.”

“After characterizing the performance of a number of competing vapor HF etch methodologies, we selected SPTS’ Primaxx reduced-pressure, dry technology because it extends our existing process capability significantly and offers enhanced compatibility with materials of interest. Leti intends to lead the way in developing MEMS devices on 300mm formats, and to achieve this we are partnering with industry leaders such as SPTS, who have the specialist process knowledge needed to transfer our 300mm MEMS developments to high-volume production,” added Fabrice Geiger, Head of the Silicon Technologies Division of CEA-Leti.

SPTS and CEA-Leti entered into a two-year agreement that will encompass full performance characterization and process optimization of both the 200mm and 300mm vapor HF process modules. This collaboration will further extend the long-standing relationship between these partners who already collaborate on the development and optimization of a range of etch and deposition processes for next-generation 3D high-aspect-ratio through-silicon-via (TSV) solutions.

CVD Source Materials


December 17, 2015

Reaction materials for chemical vapor deposition (CVD) and atomic layer deposition (ALD) are typically delivered into the chamber in a gaseous form. CVD polycrystalline silicon, for example, is deposited from trichlorosilane (SiHCl3) or silane (SiH4), using the following reactions:

SiH3Cl → Si + H2 + HCl
SiH4 → Si + 2 H2

This reaction is usually performed in LPCVD systems, with either pure silane feedstock, or a solution of silane with 70–80% nitrogen. Polysilicon may be grown directly with doping, if gases such as phosphine, arsine or diborane are added to the CVD chamber.

Silicon dioxide (usually called simply “oxide” in the semiconductor industry) may be deposited by several different processes. Common source gases include silane and oxygen, dichlorosilane (SiCl2H2) and nitrous oxide (N2O), or tetraethylorthosilicate (TEOS; Si(OC2H5)4). The reactions are as follows:

SiH4 + O2 → SiO2 + 2 H2
SiCl2H2 + 2 N2O → SiO2 + 2 N2 + 2 HCl
Si(OC2H5)4 → SiO2 + byproducts

CVD source materials are typically gases, such as silane and nitrogen, but can also be liquids: There are now a larger variety of liquid sources used in the semiconductor, FPD and PV manufacturing processes.

CVD Sources

The graph above shows the different possible states of matter. There are two ways to get from a liquid to a gaseous state. The first method involves increasing the temperature while holding the pressure steady, as indicated by the arrow with the broken line. This method is commonly used in everyday settings—to boil water and convert it to steam, for example. Heating a liquid takes time, however, which makes rapid vaporization difficult. On the other hand, one can also heat the liquid in advance and then abruptly reduce the pressure, as illustrated by the arrow with the solid line. The pressure in the vaporization section of the injector can be reduced instantaneously, and this makes it possible to vaporize a liquid source instantaneously.