Category Archives: Resource Guide

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging.

It was originally introduced by Infineon in the fall of 2007. Called eWLB, or embedded wafer-level ball grid array technology, it enables all operations to be performed highly parallel at wafer level. In August of 2008, STMicroelectronics, STATS ChipPAC, and Infineon signed an agreement to jointly develop the next-generation eWLB, based on Infineon’s first-generation technology.

Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.

STATS ChipPAC’s eWLB high volume manufacturing process, for example, today includes automated wafer reconstitution (including wafer-level molding), redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 200mm and 300mm diameters can be supported.

According to a recent report from Yole Développement, the fan-out WLP (FOWLP) market will reach almost $200M in 2015, with 30% CAGR in the coming years. Yole analysts say FOWLP started volume commercialization in 2009/2010 and started promisingly, with an initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. In 2012 big fabless wireless/mobile players started slowly volume production after qualifying the technology.

Cryogenic Vacuum Pumps


December 16, 2015

Cryopumps are commonly cooled by compressed helium, though they may also use dry ice, liquid nitrogen, or stand-alone versions may include a built-in cryocooler. Baffles are often attached to the cold head to expand the surface area available for condensation, but these also increase the radiative heat uptake of the cryopump. Over time, the surface eventually saturates with condensate and thus the pumping speed gradually drops to zero. It will hold the trapped gases as long as it remains cold, but it will not condense fresh gases from leaks or backstreaming until it is regenerated. Saturation happens very quickly in low vacuums, so cryopumps are usually only used in high or ultrahigh vacuum systems.

The cryopump provides fast, clean pumping of all gases in the 10−3 to 10−9 Torr range. The cryopump operates on the principle that gases can be condensed and held at extremely low vapor pressures, achieving high speeds and throughputs. The cold head consists of a two-stage cold head cylinder (part of the vacuum vessel) and a drive unit displacer assembly. These together produce closed-cycle refrigeration at temperatures that range from 60 to 80K for the first-stage cold station to 10 to 20K for the second-stage cold station, typically.

Regeneration of a cryopump is the process of evaporating the trapped gases. During a regeneration cycle, the cryopump is warmed to room temperature or higher, allowing trapped gases to change from a solid state to a gaseous state and thereby be released from the cryopump through a pressure relief valve into the atmosphere.

Most production equipment utilizing a cryopump have a means to isolate the cryopump from the vacuum chamber so regeneration takes place without exposing the vacuum system to released gasses such as water vapor. Water vapor is the hardest natural element to remove from vacuum chamber walls upon exposure to the atmosphere due to monolayer formation and hydrogen bonding. Adding heat to the dry nitrogen purge-gas will speed the warm-up and reduce the regeneration time.

Wet Processing, including wafer cleaning, is one of the most common yet most critical processing steps in semiconductor manufacturing, since it can have a huge impact on the success of the subsequent process step. Not only does it involve the removal of organic and metal contaminants, but it must leave the surface in a desired state (hydrophilic or hydrophobic, for example), with minimal roughness and minimal surface loss – all on a growing list of different types of materials. In this webcast, experts will identify industry challenges and possible solutions, including a new concept of tailoring chemistries to dissolve very small particles rather than physically removing them.

More than 100 steps in a standard IC manufacturing process flow involve wafer cleaning or surface preparation, which include post-resist strip/ash residue removal, native oxide removal, and even selective etching. Although dry processes continue to evolve and offer unique advantages for some applications, most cleaning/surface prep processes are “wet,” involving the use of a mixture of chemicals such as hydrofluoric; hydrochloric (HCl), sulfuric or phosphoric acid; or hydrogen peroxide, along with copious amounts of deionized water for dilution and rinsing. Wafers are typically processed in a batch immersion or batch spray system or, increasingly, with a single-wafer approach. The trend is toward more dilute chemistries, aided by the use of some form of mechanical energy, such as megasonics or jet-spray processing.

An important distinction in wafer cleaning today is that the main goal is not particle removal, but some other function, such as removing native oxide or photoresist residue removal after strip/ash.

Additional Reading

Wet process technologies for scalable through silicon vias

Simple wet cleaning improvements can meet new silicon surface preparation criteria

Vacuum Pumps


December 11, 2015

Many semiconductor manufacturing process steps require a mid- to high-level of vacuum in the process chamber to operate effectively. The optimum pumping package for each application depends on the type and amount of gases to be pumped (which are typically reaction byproducts or purge gas), the chamber size, pumping speed required and ultimate pressure required.

These include CVD, silicon epitaxy, plasma etch, ion implantation, PVD/sputtering and plasma stripping. Gas loads vary from a few sccm in ion implant systems to over a hundred sccm in CVD and etch.

Typically wafers are transferred to the chamber through a load-lock. So-called “roughing” pumps — which can be rotary vane, dry pumps (claw, screw or scroll) or “Roots blowers” – are used to take the pressure from atmospheric pressures to around 10-2 to 10-3 Torr. Then high vacuum pumps, typically turbomolecular pumps or cryogenic pumps take over to achieve process-level pressure. Roughing pumps are often located in the sub-fab below the tool. Turbos and cryos are often located very close to the process chamber, inside the tool, but can also be located in the sub-fab.

Turbo pumps use rapidly spinning blades to impart direction to gas molecules, propelling them through multiple stages of increasing pressure. Magnetic bearings are used to levitate the pump drive shaft and eliminate the need for lubricating oil.

The latest primary pumping mechanism to be introduced is the regenerative pump, which uses a single, high-speed rotor to impart momentum to the gas, compressing it through several stages to atmospheric pressure.

Additional Reading

Fundamentals of Vacuum Technology

Current and future trends in vacuum process technology

Mass Flow Controllers


December 11, 2015

In plasma-etch, chemical vapor deposition and many other processes, accurate metering of gas flow into the process chamber is critical because, beyond the process wafer, all materials that participate in the etch or deposition are introduced in gas form. In a majority of these processes, two or more of these gases react to produce the essential film or passivation layer and even slight deviations in gas flow—even on the order of 1%— can cause the process to fail.

A mass flow controller (MFC) is a device used to measure and control the flow gas into the process chamber. A gas mass flow controller is designed and calibrated to control a specific type of gas at a particular range of flow rates. The MFC can be given a setpoint from 0 to 100% of its full scale range but is typically operated in the 10 to 90% of full scale where the best accuracy is achieved. The device will then control the rate of flow to the given setpoint. MFCs can be either analog or digital.

All mass flow controllers have an inlet port, an outlet port, a mass flow sensor and a proportional control valve. The MFC is fitted with a closed loop control system which is given an input signal by the operator (or an external circuit/computer) that it compares to the value from the mass flow sensor and adjusts the proportional valve accordingly to achieve the required flow. The flow rate is specified as a percentage of its calibrated full scale flow and is supplied to the MFC as a voltage signal.

While numerous technologies have been developed to accomplish gas flow metering, the semiconductor market has focused largely on two: the thermal- based mass flow controller (MFC) and the more recently introduced pressure-based flow controller.

Today, 1% accuracy is required for challenging applications and Pewsey believes we will soon see a requirement for 0.5% accuracy. Tighter flow repeatability is also required for chamber matching.

New MFC designs feature real-time rate-of-decay flow error detection technology to continually test for changes in the device’s performance. Data can be used to improve accuracy at critical low-flow set points, set up alarm limits for critical performance parameters and monitor trends for predictive maintenance.

Additional Reading

Real time gas flow monitoring improves mass flow controller performance in wafer fab

Packaging Equipment


December 11, 2015

Every electronic device — whether it is an integrated circuit, an LED, a MEMS device, a passive component or anything else — must be connected to the outside world at some point and this requires a series of process steps to connect the “wiring” and protect the device, typically in some kind of encapsulant.

Wafers of consisting of hundreds or thousands of Individual components are cut up through a process known as dicing or “singulation,” typically by attaching the wafer to a plastic wafer carrier and cutting them with a high speed saw. Many different types of packaging technologies exist, but individual die are typically placed on a leadframe or flip chip substrate; the die attachment process is known as die bonding. This involves a machine known as a die bonder and an electrically conductive die adhesive

The next step is wire bonding, where a gold or copper wire is bonded to the contact pads on the wafer and an I/O pin on the leadrame (or, in the case of flip chip bonding, a ball bond connects the bonding pad on the chip to the substrate, and an underfill adhesive is “jetted’ in to fill voids).

After the chip is electrically connected to the carrier, it is encapsulated in the familiar black epoxy, or an alternative method of protecting the device.

Ion Implantation


December 11, 2015

Ion implantation is a materials engineering process by which ions of a material are accelerated in an electrical field and directed into the wafer, typically to form the source and drain regions of the transistor.

Ion implantation equipment typically consists of an ion source, where ions of the desired element are produced, an accelerator, where the ions are electrostatically accelerated to a high energy, and a target chamber, where the ions impinge on a target, which is the material to be implanted. Thus ion implantation is a special case of particle radiation. Each ion is typically a single atom or molecule, and thus the actual amount of material implanted in the target is the integral over time of the ion current. This amount is called the dose. The currents supplied by implanters are typically small (microamperes), and thus the dose which can be implanted in a reasonable amount of time is small. Therefore, ion implantation finds application in cases where the amount of chemical change required is small.

Typical ion energies are in the range of 10 to 500 keV (1,600 to 80,000 aJ). Energies in the range 1 to 10 keV (160 to 1,600 aJ) can be used, but result in a penetration of only a few nanometers or less. Energies lower than this result in very little damage to the target, and fall under the designation ion beam deposition. Higher energies can also be used: accelerators capable of 5 MeV are common. However, there is often great structural damage to the target, and because the depth distribution is broad, the net composition change at any point in the target will be small.

The energy of the ions, as well as the ion species and the composition of the target determine the depth of penetration of the ions in the solid: A monoenergetic ion beam will generally have a broad depth distribution. The average penetration depth is called the range of the ions. Under typical circumstances ion ranges will be between 10 nanometers and 1 micrometer.

Accelerator systems for ion implantation are generally classified into medium current (ion beam currents between 10 μA and ~2 mA), high current (ion beam currents up to ~30 mA), high energy (ion energies above 200 keV and up to 10 MeV), and very high dose (efficient implant of dose greater than 1016 ions/cm2).

Dopant ions such as boron, phosphorus or arsenic are generally created from a gas source, so that the purity of the source can be very high.

One prominent method for preparing silicon on insulator (SOI) substrates from conventional silicon substrates is the SIMOX (separation by implantation of oxygen) process, wherein a buried high dose oxygen implant is converted to silicon oxide by a high temperature annealing process.

Suppliers of ion implanters include Applied Materials, Axcelis and High Energy Corp.

Additional Reading

Leveraging ion implant process characteristics to facilitate 22nm devices

Threshold voltage tuning for 10nm and beyond CMOS integration

How to verify incident implant angles on medium current implants

Packaging Materials


December 11, 2015

According to a newly released report from SEMI and TechSearch International, the $18 billion semiconductor packaging materials market will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC leadframes, underfill, and copper wire. Segments such as wafer-level packaging (WLP) dielectrics will experience stronger unit volume growth over the same timeframe. Packaging materials include laminate substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and thermal interface materials.

Packaging materials are a key enabler to increasing the functionality of thinner, smaller packages consumed in smart phones and other mobile products. Many options are currently available to meet form factor requirements for mobile products such as stacked-die chip scale package (CSP), land grid array (LGA) and fine pitch ball grid array (FBGA) packages, package-on-package (PoP), wafer-level package (WLP), Quad Flat No-lead (QFN) and other packages, using both wirebond and flip chip interconnects.

Key trends include:

  • FO-WLP is emerging as a disruptive technology, changing the demand for the types of packaging materials used in the industry
  • Need for WLP dielectric materials for multi-layer redistribution layers
  • New materials for laminate substrates and underfill to pitch decreasing pitch and bump height trends in flip chip packaging
  • Improved mold compounds for warpage control and package reliability
  • For QFN packaging, cost optimization through enhanced designs and reduced plating area; higher lead counts (routable); improved power dissipation
  • Continued growth in copper and silver wire
  • Materials and processes compatible with tighter tolerances for higher density leadframes and substrate packaging, and for compact multi-die system-in-package (SiP) configurations

Constrained industry growth and the trend towards lower-cost electronics have reshaped the packaging material supplier landscape. Changes in material sets, the emergence of new package types, and cost reduction pressures have resulted in recent consolidation in various material segments. In addition, materials consumption in some segments is declining given the changes in package form factors and the trend towards smaller, thinner packaging.

Materials


December 11, 2015

Beyond the wafers themselves, the semiconductor industry employs thousands of different kinds of materials. These range from the materials used in wafer manufacturing — chemicals and gases, photoresists and developers, anti-reflection coatings, CMP slurries, adhesion promoters, etc. — to the materials used in the manufacturing equipment and the wafer carriers. On the packaging side, materials include laminate substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and thermal interface materials.

The market for semiconductor materials is on the same level as capital equipment. In 2015, SEMI reported that the total wafer fabrication materials and packaging materials markets in 2014 were $24.0 billion and $20.4 billion, respectively. Comparable revenues for these segments in 2013 were $22.7 billion for wafer fabrication materials and $20.4 billion for packaging materials. The wafer fabrication materials segment increased 6 percent year-over-year, while the packaging materials segment remained flat. However, if bonding wire were excluded from the packaging materials segment, the segment increased more than 4 percent last year. The continuing transition to copper-based bonding wire from gold is negatively impacting overall packaging materials revenues.

For the fifth consecutive year, Taiwan was the largest consumer of semiconductor materials due to its large foundry and advanced packaging base, totaling $9.8 billion. Japan claimed the second spot during the same time. Annual revenue growth was the strongest in the Taiwan market. The materials market in North America had the second largest increase at 5 percent, followed by China, South Korea and Europe. The materials markets in Japan and Rest of World were flat relative to 2013 levels. (The ROW region is defined as Singapore, Malaysia, Philippines, other areas of Southeast Asia and smaller global markets.)

Etch


December 11, 2015

“Dry” (plasma) etching is used for circuit-defining steps, while “wet” etching (using chemical baths) is used mainly to clean wafers. Dry etching is one of the most frequently used processes in semiconductor manufacturing. Before etching begins, a wafer is coated with photoresist or a hard mask (usually oxide or nitride) and exposed to a circuit pattern during photolithography. Etching removes material only from the pattern traces. This sequence of patterning and etching is repeated multiple times during the chip making process.

Etch processes are referred to as conductor etch, dielectric etch, or polysilicon etch to indicate the types of films they are remove from the wafer. For example, dielectric etch is involved when an oxide layer is etched to leave “oxide isolators” separating devices from each other; polysilicon etch is used to create the gate in a transistor; dielectric etch is employed to etch via holes and trenches for metal conductive paths; and metal etch removes aluminum, tungsten, or copper layers to reveal the pattern of circuitry at progressively higher levels of the device structure.

Plasma etching is performed by applying electromagnetic energy [typically radio frequency (RF)] to a gas containing a chemically reactive element, such as fluorine or chlorine. The plasma releases positively charged ions that bombard the wafer to remove (etch) materials and chemically reactive free radicals that react with the etched material to form volatile or nonvolatile byproducts. The electric charge of the ions directs them vertically toward the wafer. This produces the almost vertical etch profiles essential for the miniscule features in today’s densely packed chip designs. Typically, high etch rates (amount of material removed in a given time) are desirable.

Process chemistries differ depending on the types of films to be etched. Those used in dielectric etch applications are typically fluorine-based. Silicon and metal etch use chlorine-based chemistries. A specific etch step may be performed on one or more film layers. When multiple layers are involved and also when the etch process must stop precisely on a particular layer without damaging it, the selectivity of the process becomes important. Selectivity is the ratio of two etch rates: the rate for the layer to be removed and the rate for the layer to be protected (e.g. mask or stop layer). Higher selectivities are usually desirable.

In reactive ion etching (RIE), described above, the objective is to optimize the balance between physical and chemical etching such that physical bombardment (etch rate) is sufficient to remove the requisite material while appropriate chemical reactions occur to form either easily exhausted volatile byproducts or protective deposits on the remainder (selectivity and profile control). Magnetically enhanced RIE can aid processing by increasing ion density without increasing ion energy (which can damage the wafer).

Ideally, the etch rate is the same (uniform) at all points on a wafer. The degree to which it might vary at different points on the wafer is known as non-uniformity (or microloading) and is usually expressed as a percentage. Minimizing non-uniformity and microloading are important objectives in etching.

Source: Applied Materials

Additional Reading

Moving atomic layer etch from lab to fab