Category Archives: Wafer Inspection


Optimized settings for DI water pressure at CMP and careful analysis of interconnect layout are used to improve quality on a complex analog design.


Triboelectricity is defined as a charge of (static) electricity generated by friction. The concept was first applied in the 1940s for electrostatic painting and is now widely used in photocopy machines. This phenomenon becomes a concern in wafer manufacturing processes since water is a polar molecule and deionized water (~18MOhm) is a good insulator [1, 2].

Our investigation into circuit damage was initiated by a finding of high leakage from a single transistor within a complex analog design. Electrical and physical analysis of a failing site revealed a halo image on a TEM micrograph, suggesting that the area of highest electric field under the poly gate had been damaged (FIGURE 1).

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Wafer signature – fab root cause

After insuring there was no quality risk (with HTOL and ELFR reliability testing), focus was placed on identi- fying the physical root cause, understanding why the failures were only occurring on a single transistor, and developing a design rule to reduce the risk on future products. Examination of wafer yield maps revealed fallout of less than 500 parts per million (ppm) in a distinctive geometric pattern with failing die at unique radius from the wafer center. Discussions with fab process experts within TI revealed that the geometric pattern aligned with positions of DI water jets on a single wafer oxide chemical mechanical planarization (CMP) tool and that the problem correlated to use of high DI water pressure (60psi) during wafer transfer operation.

Subsequent experiments proved that transistor damage was occurring when DI water was used to elevate the (inverted) wafer from the load chuck to the polish head with jets of water causing static discharge in distinct locations (FIGURES 2, 3). Interim corrective action was taken to match the DI water pressure to the recommended setting of 20psi, with verification provided by both passive data and experimental results [3].

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Since static electricity in triboelectric charging is caused by friction, we can apply the Bernoulli principle to estimate the relative change in static charge when dropping water pressure from 60psi to 20psi (Equation 1). This principle states that the sum of energy (kinetic and potential) in a fluid under steady flow must be equal at all points along the stream. In the case of water being ejected from a fixed nozzle, this would require that a drop in pressure (potential energy) results in a drop in velocity (kinetic energy) thereby reducing friction and static charge.

Equation 1: Bernoulli principle

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v is the fluid flow (m/s)
g is the value of acceleration due to gravity (9.81m/s2) z is the orifice size
p is the pressure (pascals)
ρ is the density of water (1000 kg/m3)

Solving for relative difference, we find that velocity is a function of pressure, such that reducing pressure from 60psi to 20psi will decrease the velocity by about 40 percent. Thus, we can predict a corresponding drop in static charge due to friction by the same amount. The relative difference in charge was validated by using a surface photovoltage (SPV) tool, which is a method of monitoring the potential of a semiconductor surface [4], FIGURE 4.

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Tool ‘fingerprint’ analysis

Now that a physical explanation for how excess static charge was being applied to the face of product wafers had been defined, the next step was to understand why the resulting damage to the product circuit was always observed in a specific transistor (as opposed to being randomly distributed throughout the circuit). Through yield map signature analysis of the diagonal clusters of product die with a revised test screen, it was noted that while the clusters of failing die appeared at distinct radius dimensions from wafer center, their orientations were not fixed and, at first pass, seemingly random. However, upon closer inspection of the load chucks (FIGURES 2, 3), it was found that the water jets (appearing as a ‘slit’ style nozzle) had fixed orientations that were different from tool to tool.

This information led to an effort of correlating the nozzle position on each CMP tool to the orientation of diagonal clusters in the stacked yield wafer maps. This comparison made it possible to map yield loss sites from individual wafers to specific tools, and to identify that the damage was taking place at a specific layer for the product (second dielectric CMP, after metal-1).

Capacitive coupling

With the knowledge that the source of the physical damage was coming from triboelectric charging at one oxide CMP step , a working theory was created to show how the electric charge could find a path to ground from the front side (DI water jet) to the backside (grounded wafer chuck) of the wafer (FIGURE 5).

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Design considerations

In a design of more than 180 thousand transistors, it was significant that all failures mapped to a single NMOS transistor. This device was one of six identical structures, a two finger minimum sized 5V NMOS and the device was isolated from any external connections so charge coupling from an external pin was eliminated as a potential cause. Also, a review of metal-to-gate antenna design rules confirmed that there were no violations within the failing array and metal to gate ratios were well within the specification, with 10X margin. Since it was unlikely that a traditional antenna was the cause of the gate damage, additional aspects of the layout needed investigation [5].

Two areas of concern at the metal-1 layer under second dielectric were minimum metal spacing and adjacent metal routes for parallel lines. Investigation of the layout and design rules at this layer showed that minimum spacing of parallel lines was smaller than that of other metal layers, which would make the capacitance coupling between metal lines at this layer more significant.

Further analysis of the adjacent metal showed that this one transistor had a considerable amount of floating metal (prior to subsequent metal routing) adjacent to its gate metal compared to the five adjacent transistors. A model of capacitance between the floating metal and gate metal of the six structures showed that the LED5 transistor had a ratio more than 10:1 compared with ratios less than 1:1 for each of the other five transistors.

Our conclusion from these combined efforts was that failure of the single transistor in question was due to the unique layout of tight metal spacing and a high ratio of floating metal-to-gate metal, when under the influence of triboelectric charging from the fab CMP process.

An updated graphic (FIGURE 6) is used to show that charge is induced on the wafer (oxide) surface and coupled to the floating metal and finally, to the gate metal. The floating metal increases the effective gate metal capacitance such that it is now large enough to accumulate adequate charge to damage its gate oxide.

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To prevent this effect from impacting future designs, an electronic design automation (EDA) approach was used to define conditions which would flag combinations of metal:gate antenna ratios and proximity of gate to floating metal.


Root cause of high leakage from a single transistor within a complex analog design was proven to be due to an interaction between triboelectric charging in the wafer CMP process and the unique layout of this structure. Process modifications were performed to reduce DI water pressure during the wafer handling sequence at CMP, a test screen was developed to yield off any future failures and ELFR / HTOL reliability verification was performed to insure no quality risk on finished goods. EDA design checks have been developed to flag structures with high ratios of spacing for floating metal to gate metal for sites with significant metal antenna ratios.


Our thanks to several members of TI who were instrumental in identifying root cause and solutions. These include Dan Clavet, Scott Kolda, Aaron Dries, and Chris Qualey from MaineFab, Jonathan Shu and Michelle Hartsell of SVA Quality, Bill McIntyre of SVA-MDP, Dinh Nguyen of SVA- MLP, Nam Nguyen and Chris S Pereira of ATI, and Mikko Loikkanen of SVA-MLP Design.


1. Dela Cruz, W.A.; Marcelo, M.L.D.; Borlongan, M.A.B., “Preventing arcing damage on radio frequency device wafer by

controlling ESD resistivity level of water for saw and wash,” 29th Electrical Overstress/Electrostatic Discharge Symposium, 2007. EOS/ESD, vol., no., pp.3B.5-1, 3B.5-4, 16-21 Sept. 2007.

2. Re-Long Chiu (WaferTech) “Scrubber Clean Induced Device IDDQ Fail”, IEEE Proceedings, 2012.

3. S. Larivière (Altis Semiconductor), “Electro-static induced metal breakdown at interlayer dielectric post CMP brush clean process”. ASMC Proceedings, 2009.

4. Schroder, Dieter K. (2006). Semiconductor Material and Device Characterization. Wiley-IEEE Press. ISBN 0-471-73906-5.

5. Ackaert, J.; Greenwood, B., “Design solutions for preventing process induced ESD damage during manufacturing of inter- connects,” IC Design and Technology (ICICDT), 2010 IEEE Inter- national Conference on , vol., no., pp.98,101, 2-4 June 2010.

STEPHEN SWAN is Quality Manager at TI’s MaineFab in South Portland Maine; JOSEPH WILLIAMS and ERIC EVANGELOU are mem- bers of MaineFab Product Engineering; ANN CONCANNON (DMTS) is a member of TI Analog Labs in Santa Clara CA; JIM OHANNES is manager of the TI Design Center in South Portland ME.

Wet Processing, including wafer cleaning, is one of the most common yet most critical processing steps in semiconductor manufacturing, since it can have a huge impact on the success of the subsequent process step. Not only does it involve the removal of organic and metal contaminants, but it must leave the surface in a desired state (hydrophilic or hydrophobic, for example), with minimal roughness and minimal surface loss – all on a growing list of different types of materials. In this webcast, experts will identify industry challenges and possible solutions, including a new concept of tailoring chemistries to dissolve very small particles rather than physically removing them.

More than 100 steps in a standard IC manufacturing process flow involve wafer cleaning or surface preparation, which include post-resist strip/ash residue removal, native oxide removal, and even selective etching. Although dry processes continue to evolve and offer unique advantages for some applications, most cleaning/surface prep processes are “wet,” involving the use of a mixture of chemicals such as hydrofluoric; hydrochloric (HCl), sulfuric or phosphoric acid; or hydrogen peroxide, along with copious amounts of deionized water for dilution and rinsing. Wafers are typically processed in a batch immersion or batch spray system or, increasingly, with a single-wafer approach. The trend is toward more dilute chemistries, aided by the use of some form of mechanical energy, such as megasonics or jet-spray processing.

An important distinction in wafer cleaning today is that the main goal is not particle removal, but some other function, such as removing native oxide or photoresist residue removal after strip/ash.

Additional Reading

Wet process technologies for scalable through silicon vias

Simple wet cleaning improvements can meet new silicon surface preparation criteria

Wafer Inspection

December 11, 2015

Wafers need to be inspected at many stages throughout the manufacturing process. Particles and defects need to be detected and classified. Features need to be measured in both the x, y and z direction (critical dimensions and film thickness, for example). Film stoichiometry needs to be measured. Wafer warpage and bow must be evaluated and compensated for. Film stress (either tensile or compressive) is another important measurand as is dopant concentration, adhesion, and dozens if not hundred of other parameters. Variations across the wafer, within each die and die-to-die are also important.

Wafer inspection — also called metrology — is mostly used for process control, to make sure processes are not drifting out of control, As such, measurements are made after each process step — or more infrequently if at all possible since there is a cost associated with every inspection step in terms of capital equipment required, reduced throughput and added particles from increased handling.

Of course, more advanced characterization techniques are also needed for process development and failure analysis.

New inspection challenges include the need to measure more complex device structures such as those found in FinFETs and 3D NAND. The industry is also pushing a wide array of new materials into production, which brings a new set of challenges since each type of material has unique properties when it comes to reflection, refraction, adhesion, stress, etc.

The push to smaller dimensions and thinner films means smaller defects and variations become more important, which often pushes the accuracy, resolution and repeatability limits of today’s measurement tools.

The most common type of wafer inspection tool is the optical microscope. Although still used today for macro inspection, the very small dimension on today’s wafers can only be measured by more advanced means, most notably the scanning electron microscope and the transmission electron microscope. Other commonly used tools include ellipsometers to measure film thickness.

For failure analysis, even more sophisticated surface analysis tools are required, including  ESCA, Auger, EDAX, and Rutherford Backscattering (RBS), among many others.

SAN JOSE, Calif. — Nov. 11, 2015 — Ultratech, Inc., a supplier of lithography, laser-processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HB-LEDs), as well as atomic layer deposition (ALD) systems, today introduced the Superfast 4G+  in-line, 3D topography inspection system. Ultratech’s new 4G+ system builds on the field leadership of the Superfast 4G, providing the industry’s highest-productivity and lowest-cost solution for high-volume manufacturing. The Superfast 4G+ system’s patented coherent gradient sensing (CGS) technology enables Ultratech customers to use a single type of wafer inspection tool to measure patterned wafers across the entire fab line at the lowest cost. Ultratech plans to begin shipping the Superfast 4G+ systems in the first quarter of 2016.

Superfast 4G+ features include:

  • Direct, front-side 3D topography measurement for opaque and transparent stacks patterned wafers
  • 150 wph, the highest industry 3D in-line inspection throughput with the smallest footprint
  • 1-mm edge exclusion enabling full-wafer pattern inspection and thin-film 3D process control
  • Large bow option for in-line manufacturing control of highly bowed wafers without impacting throughput

Damon Tsai, Ultratech Asia Director for Inspection Systems, said, “Our current leadership position in in-line 3D inspection at advanced memory and foundry manufacturers with Superfast 4G has provided us with a tremendous learning environment. Our partners have helped us develop new hardware capabilities like the ‘Recipe Driven Range Control,’ an innovative high-throughput, large bow optical option on board the Superfast 4G+, as well as new fleet management performance metrics. The inherently simple design of the CGS technology is enabling us to rapidly deliver new capabilities and performance improvements over more complex optical solutions.”

Based on patented CGS technology, Ultratech’s Superfast 4G+ inspection system provides the industry’s highest throughput (150 wph) with the lowest cost-of-ownership compared to competing systems. The direct, front-side 3D topography measurement capability is well-suited for patterned wafer applications such as lithography feed-forward overlay distortion and edge-defocus control as well as thin-film deposition stress and planarization control. Delivering a 2X improvement in performance with fleet matching TMU (Total Measurement Uncertainty), along with the ability to measure opaque and transparent stacks on patterned wafers, the Superfast 4G+  provides cost-effective technology to address the critical needs of its global customers. In addition, leveraging the same breakthrough CGS optical module, the Superfast 4G+ is available as a field upgrade of the Superfast 4G.