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By Cherry Sun

“We are living in a digital world where semiconductors are taken for granted, AI is bringing semiconductors back into the deserved spotlight, and now we are witnessing the dawn of the Cognitive Era enabled by semiconductors,” SEMI president and CEO Ajit Manocha said to an audience of more than 500 during his presentation – Rebirth of the Semiconductor Industry – at the First Global IC Entrepreneur Conference.

Speaking at the Shanghai event in mid-December, Manocha recalled how, when he first entered the semiconductor industry in the 1980s, semiconductors revenue topped out at about $10 billion. Now, with sales having swelled to a staggering $450 billion, the industry is on a much faster growth track. Revenue could reach $500 billion by the end of 2020 and trillions of dollars by 2030.

Over the past two decades, chips have given rise to social media and e-commerce powerhouses such as Google, Facebook, and Alibaba. All rely on heavily on chips, the engines of data centers across all industries. Wave after wave of technology innovation have been powered by semiconductors – from mainframe computers in the 1970s, personal computers in the 1980s, the Internet in the 1990s, and mobile and social networking in the early 20th century, to the current shining stars of technology such as IoT, big data, new memory, virtual reality, autonomous driving and artificial intelligence, Manocha said. New applications across areas such as smart manufacturing and digital healthcare are stoking the latest round of semiconductor growth.

The rise of AI, like all the technologies before it, has renewed the semiconductor industry once again with its promise to drive growth of all industries worldwide, Manocha said. Five years ago, IoT was but a gleam in a technologist’s eye, more hype than reality with doubt about its viability running deep. Today, with about 60 percent of people in the world connected to the Internet, the enormous promise and potential of IoT is flowering.

Industry growth will explode as the melding of AI and IoT birth countless applications and innovations in SMART transportation (0 emissions; 0 fatalities; 0 congestion), smart sensors (agriculture, infrastructure, healthcare) and SMART “Everything” (people, devices, homes, cities, industries, and the list goes on). Indeed, AI is now widely recognized as a chief growth driver of the semiconductor industry well into the future, with semiconductor technology at the core of AI innovation, he said.

Semiconductors are thrusting the fifth industrial revolution into the fast lane. China’s much-anticipated rise as an industry powerhouse over the next few years will only accelerate industry growth, turning current disruptions into future opportunities as SEMI China continues to cultivate connection, collaboration and innovation in China’s fast-growing semiconductor sector.

Cherry Sun is a marketing manager at SEMI China. 

Date: Tuesday, January 29, 2019 at 1:00 pm EST

Free to attend

Length: Approximately one hour

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In semiconductor manufacturing, traditional root cause analysis using FDC summary data is not always effective in solving complex issues, especially when the defect signals are too subtle to detect. Full trace analytics enables the discovery of these hidden signals.  This allows fab engineers to accurately pinpoint the root causes of yield-impacting issues. This webcast will discuss several use cases to showcase how advanced full trace analytics can help not only in provide accurate results, but can also simplify the root cause analysis process and reducing time-to-root-cause, resulting in better yields, lower production costs and increased engineering productivity.
In this LIVE webcast, BISTel’s Chief Product Management Officer, Gabe Villareal will discuss how BISTel is leading the industry with its new full trace analytics to simply root cause analysis, which enables fab engineers to pinpoint the issues than impact yield and productivity quicker than ever. Full trace analytics enables the comprehensive examination of process trace data to allow the detection of abnormalities and deviations to the finest details.

What You’ll Learn:

  • Learn how to improve yield and reduce risk with new full trace analytics to simply root cause analysis.
  • Hear why traditional root cause analysis using FDC summary data is not always effective in solving complex issues, especially when the defect signals are too subtle to detect.
  • Understand how full trace analytics enables the comprehensive examination of process trace data to allow the detection of abnormalities and deviations to the finest details.
  • Learn how these techniques can help not only provide accurate results, but can simplify the root cause analysis process and reduce time-to-root-cause. This results in better yields, lower production costs and increased engineering productivity.

About the Speaker:

Gabe Villareal, Vice President, Global Product Management Group, BISTel

As Vice President Global Product Management (GPM) at BISTel, Mr. Villareal leads the company’s product development programs. He is largely responsible for bridging BISTel’s semiconductor industry leading Equipment Engineering Systems (EES) and its new adaptive intelligence (AI) applications for smart manufacturing.  Together,  these intelligent manufacturing solutions detect, analyze and predict answers  to everyday manufacturing challenges quicker and more effectively than ever.  Gabe and his team focus on helping engineers improve quality, productivity, wafer yields, and overall manufacturing effectiveness. For more than 20 years, Gabe has led engineering and product development teams to develop winning Equipment Engineering System (EES) and analytical solutions for the global semiconductor and FPD manufacturing industries. With the meteoric rise of IIoT, Big Data, Edge and Cloud Computing, Gabe and his team are being called on more than ever to support the semiconductor engineering community as they navigate in the age of AI and industry.

Sponsored by:

BISTel is a leading provider of real-time, engineering and automation solutions for the global semiconductor, and electronics industries. Its Equipment Engineering Systems (EES) and adaptive intelligence (AI) solutions for smart manufacturing are shaping the factories of the future,  by connecting data driven manufacturing organizations to better detect, analyze, and predict real-time to changing manufacturing conditions. Consequently, manufacturers can realize major costs reductions, plant wide operational efficiencies, improved yields and unmatched engineering productivity.  BISTel manufacturing solutions collect and manage data, monitor the health of equipment, optimize process flows, analyze large data and quickly identify root cause failures to mitigate risk for engineers and manufacturers worldwide.  Founded in 2000, BISTel has more than 377 employees worldwide. The company is headquartered in South Korea, with offices in California, China, Singapore and Texas.  BISTel has a deep customer following in semiconductor, FPD, and rechargeable batteries, PCB/SMT manufacturing as well as automotive, and steel manufacturing. Its core solutions include:

  • Fault detection & classification solutions that include equipment recipe management, advanced process control, equipment performance analysis and more.
  • Powerful data mining, root cause analysis & pattern analysis, as well as a new Chamber Matching application to offer the industry its most comprehensive set of data analytics tools on the market.
  • Innovative new predictive analytics, predictive maintenance, real-time product & facility monitoring identify issues before they happen.

For more more information contact [email protected] or [email protected]

A new collaborative study led by a research team at the Department of Energy’s Pacific Northwest National Laboratory and University of California, Los Angeles could provide engineers new design rules for creating microelectronics, membranes, and tissues, and open up better production methods for new materials. At the same time, the research, published in the journal Science, helps uphold a scientific theory that has remained unproven for over a century.

Just as children follow a rule to line up single file after recess, some materials use an underlying rule to assemble on surfaces one row at a time, according to the study done at PNNL, the University of Washington, UCLA, and elsewhere.

Nucleation — that first formation step — is pervasive in ordered structures across nature and technology, from cloud droplets to rock candy. Yet despite some predictions made in the 1870s by the American scientist J. Willard Gibbs, researchers are still debating how this basic process happens.

The new study verifies Gibbs’ theory for materials that form row by row. Led by UW graduate student Jiajun Chen, working at PNNL, the research uncovers the underlying mechanism, which fills in a fundamental knowledge gap and opens new pathways in materials science.

Chen used small protein fragments called peptides that show specificity, or unique belonging, to a material surface. The UCLA collaborators have been identifying and using such material-specific peptides as control agents to force nanomaterials to grow into certain shapes, such as those desired in catalytic reactions or semiconductor devices. The research team made the discovery while investigating how a particular peptide — one with a strong binding affinity for molybdenum disulfide — interacts with the material.

“It was complete serendipity,” said PNNL materials scientist James De Yoreo, co-corresponding author of the paper and Chen’s doctoral advisor. “We didn’t expect the peptides to assemble into their own highly ordered structures.”

That possibly happened because “this peptide was identified from a molecular evolution process,” adds co-corresponding author Yu Huang, a materials scientist at UCLA. “It appears nature does find its way to minimize energy consumption and to work wonders.”

Row by row

The transformation of liquid water into solid ice requires the creation of a solid-liquid interface. According to Gibbs’ classical nucleation theory, although turning the water into ice saves energy, creating the interface costs energy. The tricky part is the initial start — that’s when the surface area of the new particle of ice is large compared to its volume, so it costs more energy to make an ice particle than is saved.

Gibbs’ theory predicts that if the materials can grow in one dimension, meaning row by row, no such energy penalty would exist. Then the materials can avoid what scientists call the nucleation barrier and are free to self-assemble.

There has been recent controversy over the theory of nucleation. Some researchers have found evidence that the fundamental process is actually more complex than that proposed in Gibbs’ model.

But “this study shows there are certainly cases where Gibbs’ theory works well,” De Yoreo said.

Previous studies had already shown that some organic molecules, including peptides like the ones in the Science paper, can self-assemble on surfaces. But at PNNL, De Yoreo and his team dug deeper and found a way to understand how molecular interactions with materials impact their nucleation and growth.

They exposed the peptide solution to fresh surfaces of a molybdenum disulfide substrate, measuring the interactions with atomic force microscopy. Then they compared the measurements with molecular dynamics simulations.

De Yoreo and his team determined that even in the earliest stages, the peptides bound to the material one row at a time, barrier-free, just as Gibbs’ theory predicts.

The atomic force microscopy high imaging speed allowed the researchers to see the rows just as they were forming. The results showed the rows were ordered right from the start and grew at the same speed regardless of their size — a key piece of evidence. They also formed new rows as soon as enough peptide was in the solution for existing rows to grow; that would only happen if row formation is barrier-free.

Better control

This row by row process provides clues for the design of 2D materials. Currently, to form certain shapes, designers sometimes need to put systems far out of equilibrium, or balance. That is difficult to control, said De Yoreo.

“But in 1D, the difficulty of getting things to form in an ordered structure goes away,” he added. “Then you can operate right near equilibrium and still grow these structures without losing control of the system.”

It could change assembly pathways for those engineering microelectronics or even bodily tissues.

Huang’s team at UCLA has demonstrated new opportunities for devices based on 2D materials assembled through interactions in solution. But she said the current manual processes used to construct such materials have limitations, including scale-up capabilities.

“Now with the new understanding,” said Huang, “we can start to exploit the specific interactions between molecules and 2D materials for automatous assembly processes.”

The next step, said De Yoreo, is to make artificial molecules that have the same properties as the peptides studied in the new paper — only more robust.

At PNNL, he and his team are looking at stable peptoids, which are as easy to synthesize as peptides but can better handle the temperatures and chemicals used in the processes to construct the desired materials.

Don’t worry if you missed this – NOW AVAILABLE on-demand! Register to View:

Date: Thursday, December 13, 2018 at 10:00 AM Pacific / 1:00 PM Eastern

Free to attend

Length: Approximately one hour

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As digital-centric scaling pursues solutions in 3D device architectures such as gate-all-around (GAA) transistors, most applications in new leading-edge growth markets such as Edge AI/ML, IoT, automotive and 5G mmWave demand post-bulk processing power and also next-generation analog and RF performance. This webinar is an overview of production-proven fully-depleted silicon-on-insulator (FD-SOI), the only post-bulk planar transistor technology. We will explain and demonstrate how FD-SOI delivers FinFET-like performance, excellent mismatch and noise characteristics and best-in-class Ft and Fmax required for energy-efficient mmWave applications.

What You’ll Learn:

  • Learn how fully-depleted silicon-on-insulator (FD-SOI) delivers FinFET-like performance, excellent mismatch and noise characteristics and best-in-class Ft and Fmax required for energy-efficient mmWave applications.
  • Hear why most applications in new leading-edge growth markets such as Edge AI/ML, IoT, automotive and 5G mmWave demand post-bulk processing power and also next-generation analog and RF performance.
  • Understand why production-proven FD-SOI is the only post-bulk planar transistor technology.


Dr. Jamie Schaeffer – Jamie Schaeffer is Senior Director of Product Offering Management at GLOBALFOUNDRIES.  Schaeffer is currently responsible for the FDXTM product offerings, including 22FDX® and 12FDXTM, which enable differentiated solutions for mobile, wireless networking, Internet of Things and automotive markets. Prior to this, Schaeffer had an extensive career in technology development at GLOBALFOUNDRIES, Freescale Semiconductor, and its predecessor Motorola Semiconductor Products Sector.  Schaeffer helped lead the development and transfer into volume manufacturing of the 32nm and 28nm technologies and his earlier work in the semiconductor industry has been recognized with numerous invited talks and a Distinguished Innovator award for his contributions to technology innovation while at Freescale Semiconductor. Schaeffer holds a bachelor’s degree in materials science and engineering from Cornell University and a Ph.D. in materials science and engineering from The University of Texas at Austin.

Dr. Brian Chen – Brian Chen currently serves as Director of FDXTM Offering Management at GLOBALFOUNDRIES.  Brian has worked in engineering, field, marketing, and operational roles at EDA, IDM, and foundry companies.  Previous products under his management include circuit simulation tools, Liberty library characterization product, device characterization and modeling software, and low-frequency noise measurement system.  Brian received his Ph.D and M.S. degrees in electrical and computer engineering from the Georgia Institute of Technology, U.S., and M.S. and B.S. degrees in engineering from Saint-Petersburg Electrotechnical University, Russia.

About Our Sponsor:

GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Investment Company.

Silicon Integration Initiative, an integrated circuit research and development joint venture, announced today that IBM and GLOBALFOUNDRIES have contributed patented technology to support the Si2 Unified Power Model standard, the industry’s first significant power model enhancement in many years.

Early stage estimation of System on Chip power consumption is fundamental to ensuring new SoC designs meet or exceed power specifications when fabricated. For a credible estimate, the power models must comprehend the target implementation technology and circuitry, along with voltage and temperature conditions. At the same time, power estimation results are needed quickly to perform rapid “what if” scenarios.

UPM’s multi-level power modeling capability provides the necessary level of modeling detail required at various stages of design. Abstract high-level equations to gate-level characterization tables can be accommodated through the same, standard interface. Beyond this, the UPM interface, upon acceptance and approval by the IEEE’s P2416 working group, will be a direct plug-in to the widely-used IEEE 1801 stub created for power models.

The IBM and GF contributions enhance UPM by providing a new and unique approach to power modeling. Rather than storing pre-characterized, process-voltage-temperature specific data, UPM models store power proxies that represent different contributors to overall power consumption, such as sub-threshold leakage, gate leakage, and dynamic power. Appropriately entitled “power contributors,” this approach vastly simplifies and reduces the power modeling effort, and allows the power model to be voltage and temperature independent, enabling a single power model to be used at a multitude of voltages and temperatures.

SoC designers using UPM with contributor-based modeling will ultimately be equipped with thermally-aware, system-level power estimation. In addition, the late-binding of specific PVT conditions at simulation run-time will provide accurate, early estimates of leakage power, which increases exponentially with increasing temperature. The donated technology covers key aspects of contributor-based power modeling including model abstraction, generation, compression and evaluation.

Contributor-based modeling will be fully integrated into UPM, which forms the basis for P2416, the planned IEEE standard for developing and maintaining interoperable, IC design power models. P2416 is scheduled for balloting in early 2019.

Jerry Frenkil, director of Si2 OpenStandards, said the IBM and GF contributions bolster UPM and provide P2416 with proven and ready-to-use modeling methods. “These power proxies enable voltage and temperature-independent modeling which greatly reduce the model generation and support effort,” Frenkil explained. “They also enable late binding of voltage and temperature conditions at simulation run-time, a major benefit for both IP developers and SoC designers.”

“IBM is pleased to donate this advanced modeling technology to Si2’s UPM development to facilitate interchange of IP power data,” said Dr. Leon Stok, vice president of EDA at IBM. “We have used contributor modeling internally on several generations of IBM micro-processors to great effect. We look forward to seeing UPM contributor models being provided by IP block developers so that entire systems, consisting of both internal and external IP, can be modeled efficiently using a common modeling standard. Additionally, the combination of power contributors and multi-level modeling structures promises major cost and resource improvements in creating and supporting IP power models.”

“UPM directly addresses a major industry need—accurate and efficient system-level power models,” said Richard Trihy, senior director of design enablement at GF. “Since IP providers need only produce a single model for a multitude of PVT points, these models enable significant productivity gains in model generation. Our clients will also get a good early estimate of their systems’ total power, including leakage, which can operate at high temperatures.”

“These contributions from IBM and GF come at a fortuitous time,” said Dr. Nagu Dhanwada of IBM, chair of the IEEE P2416 Working Group and the Si2 UPM development project. “The P2416 Working Group is rapidly gathering momentum towards IEEE standardization. We anticipate going to ballot early next year.”

North America-based manufacturers of semiconductor equipment posted $2.24 billion in billings worldwide in August 2018 (three-month average basis), according to the August Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 5.9 percent lower than the final July 2018 level of $2.38 billion, and is 2.5 percent higher than the August 2017 billings level of $2.18 billion.

“Global billings of North American equipment suppliers declined in August when compared to July, although they remain above August 2017 billings,” said Ajit Manocha, president and CEO of SEMI. “Industry spending remains solid and we expect equipment expenditures in North America, China, Japan, and Taiwan to increase over their respective levels relative to the first half of the year.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

(3-mo. avg.)
March 2018
April 2018
May 2018
June 2018
July 2018 (final)
August 2018 (prelim)

Source: SEMI (, September 2018

Solid State Technology and SEMI today announced the recipient of the 2017 “Best of West” Award – BISTel for its Dynamic Fault Detection (DFD®) system. The award recognizes important product and technology developments in the electronics manufacturing supply chain. Held in conjunction with SEMICON West, the largest and most influential electronics manufacturing exposition in North America, the Best of West finalists were selected based on their financial impact on the industry, engineering or scientific achievement, and/or societal impact.

BISTel’s Dynamic Fault Detection (DFD®) system offers full trace data coverage and eliminating the need for timely and costly modeling and set up. DFD® is also a bridge to smart factory manufacturing because it integrates seamlessly to legacy FDC systems meaning customers can access the most comprehensive, and accurate fault detection system on the market. (South Hall Booth 1811).

“There’s a big emphasis in smart manufacturing at this year’s SEMICON West,” said Pete Singer, Editor-in-Chief of Solid State Technology. “The BISTel dynamic fault detection system is a great example of a fantastic smart tool now available to semiconductor manufacturers.”

About SEMI

SEMI® connects over 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMI members are responsible for the innovations in materials, design, equipment, software, devices, and services that enable smarter, faster, more powerful, and more affordable electronic products. FlexTech, the Fab Owners Alliance (FOA) and the MEMS & Sensors Industry Group (MSIG) are SEMI Strategic Association Partners, defined communities within SEMI focused on specific technologies. Since 1970, SEMI has built connections that have helped its members prosper, create new markets, and address common industry challenges together. SEMI maintains offices in Bangalore, Berlin, Brussels, Grenoble, Hsinchu, Seoul, Shanghai, Silicon Valley (Milpitas, Calif.), Singapore, Tokyo, and Washington, D.C.  For more information, visit and follow SEMI on LinkedIn and Twitter.

About Extension Media

Extension Media is a publisher of over 20 business-to-business magazines (including Solid State Technology), resource catalogs, newsletters and web sites that address high-technology industry platforms and emerging technologies such as chip design, embedded systems, software and infrastructure, intellectual property, architectures, operating systems and industry standards. Extension Media publications serve several markets including Electronics, Software/IT and Mobile/Wireless. Extension Media is a privately held company based in San Francisco, Calif. For more information, visit

3D-Micromac AG, the industry leader in laser micromachining and roll-to-roll laser systems for the semiconductor, photovoltaic, medical device and electronics markets, today introduced the microPREP™ 2.0 laser ablation system for high-volume sample preparation of metals, semiconductors, ceramics and compound materials for microstructure diagnostics and failure analysis (FA).

Built on a highly flexible platform with a small table-top footprint, the microPREP 2.0 allows for easy integration into FA workflows. Developed jointly with Fraunhofer Institute for Microstructure of Materials and Systems (IMWS), the microPREP 2.0 complements existing approaches to sample preparation such as focused ion beam (FIB) micromachining, offering up to 10,000 times higher ablation rates and therefore an order of magnitude lower cost of ownership (CoO) compared to FIB. As the first stand-alone, ultrashort pulsed laser-based tool for sample preparation, the microPREP 2.0 brings additional unique capabilities, such as enabling large-area and 3D-shape sampling to allow for more comprehensive testing of complex structures.

The microPREP™ 2.0 laser ablation system from 3D-Micromac provides high-volume sample preparation of metals, semiconductors, ceramics and compound materials for microstructure diagnostics and failure analysis.

Sample preparation an enabling step for semiconductor failure analysis

Cutting and preparing samples from semiconductor wafers, dies and packages for microstructure diagnostics and FA is an essential but time-consuming and costly step. The primary method of sample preparation used in semiconductor and electronics manufacturing today is FIB micromachining, which can take several hours to prepare a typical sample. FIB only allows for very small sample sizes, and precious FIB time is wasted by “digging” excavations needed for cross-sectional imaging in a scanning electron microscope or making a TEM lamella. Reaching larger depths or widths is severely restricted by the limited ablation rate.

3D-Micromac’s microPREP 2.0 significantly accelerates these critical steps, bringing sample preparation for semiconductor and materials research to a new level. By off-loading the vast majority of sample prep work from the FIB tool and relegating FIB to final polishing or replacing it completely depending on application, microPREP 2.0 reduces time to final sample to less than one hour in many cases.

“This award-winning tool brings unprecedented flexibility into sample prep. We at Fraunhofer IMWS are facing the need for targeted, artifact-free and most reliable preparation workflows to be able to serve our industry customers with cutting-edge microstructure diagnostics. Made for diverse techniques like SEM inspection of advanced-packaging devices, X-ray microscopy, atom probe tomography, and micro mechanics, microPREP was developed jointly with
3D-Micromac to close gaps in preparation workflows,” said Thomas Höche, Fraunhofer IMWS.

Last month, 3D-Micromac and Fraunhofer IMWS received the prestigious TUV SUD Innovation Award for their collaboration on the development of microPREP 2.0. The annual prize honors successful cooperation between small and medium-size enterprises and research institutions. It is administered by TUV SUD, a leading technical service corporation serving the industry, mobility and certification segments.

TÜV SÜD Innovation Award ceremony on June 26. From left to right: Prof. Dr. med. Thomas Hoeche, Fraunhofer IMWS; Uwe Wagner, 3D-Micromac AG; Prof. Dr. Simon Hecker, University of Munich;
Prof. Dr. Stefan Sentpali, MdynamiX AG; Pascal Russ and Andreas Russ, Simi Reality Motion Systems GmbH; Prof. Dr. Axel Stepken, TÜV SÜD AG.

Key benefits of microPREP 2.0 include:

  • Much higher ablation rate compared to FIB (by several orders of magnitude)
  • Up to an order of magnitude lower CoO compared to classical FIB workflow
  • High degree of automation due to recipe-based, ergonomic user interface
  • Extremely high energy densities can be focused in very small areas (allowing for operation in the multi-photon absorption regime needed to machine at-wavelength-transparent materials and enabling stable process windows)
  • Virtually no structural damage from local heating due to the platform’s very short pulse lengths (pico-second range)
  • Providing larger-sized samples with micron-level precision — enabling multi-site FA on whole chip or package areas in a much shorter period of time and a multitude of workflows delivering samples for various FA techniques
  • Enables the creation of samples with complicated/3D shapes to enable more comprehensive analysis of certain structures, such as through silicon vias (TSVs) or even complete systems-in-package (SiP)

Laser processing without elemental contamination

microPREP 2.0 can be used for a variety of semiconductor sample preparation applications, including: in-plane geometries and bulk samples; cross-sections; box milling (such as for diagnostics of electrical connections and 3D chip-level structures); and full line cut (for complex investigations of complete devices). Samples can be moved between microPREP 2.0 and FA tools using the same pin stubs and holders, which provides even greater ease of use and time savings.

“The growing complexity of microelectronics manufacturing is driving the need for faster, more reliable and cost-effective, and artifact-free sample preparation techniques at the micron scale,” stated Jan Klinger, chief sales officer at 3D-Micromac. “Building on our extensive expertise in laser micromachining, 3D-Micromac can now offer an optimal sample preparation solution for this market. By off-loading the coarse and time-consuming task of sample preparation to a simple and fast support tool, microPREP frees up our customers’ time to focus their efforts on fab-critical issues like trouble-shooting process and yield problems.”

Media, analysts and potential customers interested in learning more about 3D-Micromac’s laser micromachining solutions, including microPREP 2.0, are invited to visit the company at SEMICON West 2018, July 10-12 at the Moscone Convention Center in San Francisco, Calif., in South Hall, booth #1645. More information on microPREP is also available on


Date: Tuesday, June 5, 2018 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

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EUV lithography has steadily been gaining momentum in recent years and edges closer and closer to insertion in manufacturing.  While considerable progress has been made and the first uses of EUV appear imminent, there remain some difficulties that will challenge the rate and degree to which EUV can be employed.  This talk will aim to explore the patterning-related challenges that remain, summarize some of the ongoing efforts to tackle these challenges, and give an outlook towards the future.

What You’ll Learn:

  • Understand how EUV lithography has steadily been gaining momentum in recent years and edges closer and closer to insertion in manufacturing.
  • Hear about the difficulties that remain and how they will challenge the rate and degree to which EUV can be employed.
  • Find out what’s being done to tackle these challenges, and what the outlook is towards the future.

Speaker: Greg McIntyre, Director of Advanced Patterning, imec

Greg McIntyre is Director of Advanced Patterning at imec and responsible for areas related to advanced lithography equipment and process development, metrology and patterning process control, computational lithography, and exploratory patterning materials. Prior to joining imec, he was the technical lead for various areas of advanced lithography, imaging and modeling within the IBM research alliance in Albany, New York. He has published over 80 papers, won 7 best paper awards, and has launched a successful startup in the field. Prior to becoming a lithographer, Greg served as a Captain in the US Army. He holds a Ph.D. and M.S. in electrical engineering from the University of California, Berkeley, and a B.S. from the United States Military Academy at West Point.

Sponsored by LouwersHanique

Featured Products: 3D components in glass and fused silica using “Selective Laser-induced Etching” (SLE) Technologies and Modular Ultra-High Vacuum electrical and optical feedthroughs

LouwersHanique has been a leading specialist in the manufacturing of technical glass and ceramic components as well as assembly technologies for a wide variety of high-tech industries for over 60 years. We are specialized in thermal forming of glass and in the mechanical and laser processing of technical glass and technical ceramics. Our state of the art equipment and clean room facilities allow the precision manufacturing of parts and assemblies with tolerances into the (sub) micron region.

Analog Devices, Inc. (Nasdaq: ADI), has unveiled its new India headquarters for the approximately 600 Bengaluru-based staff who make up ADI India. The new 175,000 square foot facility, which houses one of ADI’s top three global design centers, will focus on developing and selling cutting edge technologies and solutions for the global automotive, industrial, healthcare, consumer, Internet of Things (IoT), security, communications, and energy markets.

“We have created a culture of innovation, collaboration and engineering excellence at ADI, encouraging our engineers to explore, learn and share while giving them opportunities to work across teams and domains so they become well-rounded experts,” said Yusuf Jamal, Senior Vice President of ADI’s Industrial, Healthcare, Consumer, and IoT Solutions and Security Group. “We have been aggressively investing in our global facilities, including a recently announced U.S. expansion in Silicon Valley, to better attract and leverage local talent and skills and this investment in ADI India will better position us to accelerate growth and impact for ADI.”

Having started as a three-person product development center in 1995, ADI India’s headcount has grown by a factor of 200 over the last twenty years to support the evolving needs of ADI’s global customers. Mirroring ADI’s transformation from a manufacturer of modules and integrated circuits (ICs) to a provider of edge-to-cloud systems, and from a focus solely on hardware to one that includes software and data analytics, ADI India counts software, artificial intelligence (AI), machine learning (ML), applications, product and test engineering, systems, and analog and mixed signal IC development among its broad suite of capabilities.

“ADI India has come a long way since its humble beginnings as an integrated circuit design center, having experienced an impressive expansion in the capabilities and range of functions being performed by our skilled employees here in Bengaluru,” said Sai Krishna Mopuri, Managing Director, ADI India. “As we move into this new facility, we plan to expand our university relations program work with reputed academic institutions, which includes fellowships, sponsorships and internship opportunities, through additional partnerships and talent acquisition from engineering colleges across the country.”