Category Archives: Uncategorized

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Sensor Fusion and the Role of MEMS in IoT

Date: Thursday May 28, 2015 at 1:00 p.m. EST

Free to attend

Length: Approximately one hour

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MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. This webcast will explore the latest trends in MEMS devices – including sensor fusion and the important role that MEMS will play in the Internet of Things (IoT). Marcellino Gemelli, Head of Business Development at Bosch Sensortec will discuss how smart systems are enabled through sensor fusion. Karen Lightman, Executive Director of MEMS Industry Group (MIG), will provide a “debrief” from the recent MEMS Technical Congress and a preview of a SEMICON West workshop focused on back-end challenges.

Speakers: 

marcellinogMarcellino Gemelli, Head of Business Development, Bosch Sensortec

Marcellino Gemelli received the ‘Laurea’ degree in Electronic Engineering at the University of Pavia, Italy in 1994, while in the Italian Army and an MBA from MIP, the Milano (Italy) Polytechnic business school. He is currently based in Palo Alto (CA) and is responsible for business development of Bosch Sensortec’s MEMS product portfolio and Bosch’s IoT wireless sensor network initiative. He previously held various engineering and product management positions at STMicroelectronics from 1995 to 2011 in the fields of MEMS, electronic design automation and data storage. He was also a contract professor for the Microelectronics course at the Milano (Italy) Polytechnic from 2000 to 2002.

Tony MassiminiTony Massimini, Chief of Technology at Semico Research Corporation

Tony has been analyzing the market for microprocessors (MPUs) and microcontrollers (MCUs) in both the computing and embedded control markets.  He is also an expert for Micro-Electrical Mechanical Systems (MEMS). Tony analyzes the MEMS market covering such topics as Sensor Fusion, smart phones, medical applications, oscillators, energy harvesting, electronic standards and the Internet of Things.  Tony is instrumental in coordinating the development of Semico’s Bill of Materials for Semico’s online MAP Model analysis tool.

Karen Lightman.jpgKaren Lightman, Executive Director, MEMS Industry Group (MIG)

Karen played a pivotal role in launching MIG in January 2001. Karen is active on the worldwide MEMS conference circuit as a keynote speaker and panelist promoting MIG’s role as the leading trade association advancing MEMS and sensors across global markets. Karen manages the operations of MIG; spearheads strategic growth; and oversees sales, public relations, marketing and outreach. Karen plays a critical role in creating the content for all MIG and MIG-partner conferences, events and programming. She is instrumental in establishing and maintaining partnerships with other international organizations to advance the MEMS industry. Karen has a BA from the University of Vermont (UVM) and a MS in Public Policy from Carnegie Mellon University. Karen and her family reside in Pittsburgh, PA.

Sponsored by Air Products 

Air Products has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  www.airproducts.com/advancing

Brewer Science, a supplier of advanced materials, processes, and equipment to the microelectronics industry, announced today the first commercial placement of a Cee 300MXD megasonic developer. This innovative developer was commissioned by MicroChem Corp., another well-known member of the microelectronics industry.

The Brewer ScienceCee 300MXD megasonic developer applies uniform acoustic energy to spinning substrates to gently dissolve and remove films and residues without damaging fragile device structures. This precision handling results in stable dimensional control of vertical profiles uniformly across the wafer surface, enabling fabrication of high-aspect-ratio structures for the MEMS, display, compound semiconductor, and advanced packaging markets. Applications include radio-frequency (RF) power, MEMS, sensors, and acoustic wave devices used for wireless communication.

“MicroChem is very pleased to team with Brewer Science on what we believe could be an enabling technology for the future,” said Michael Stan, Applications Engineering Manager for MicroChem Corp. “As the MEMS industry and integrated packaging technology continue to demand higher-aspect-ratio structures for TSV and RDL layers, enhanced development techniques will likely become mainstream. The cost-effective approach being pioneered by Brewer Science gives a supplier such as MicroChem Corp. the advantage of being able to rapidly prototype formulations and processes to meet these demands,” he added.

“The Cee 300MXD developer features state-of-the-art technology that creates a viable pathway for our customers to decrease process cycle times, reduce cost of ownership, and accelerate time to market,” said Justin Furse, Brewer Science Equipment Technology Strategist.

The Cee 300MXD megasonic developer gives customers an ideal bridge from the lab to production by allowing them to avoid significant capital investment. Our semi-automated equipment delivers quality and precision comparable to automatic multimillion-dollar tools and is suitable for low-volume prototyping with a seamless transition to high-volume manufacturing.

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Trends in Materials: The Smartphone Driver

Date: Thursday, April 30, 2015 at 1:00 p.m. EST

Free to attend

Length: Approximately one hour

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Today the semiconductor industry is driven by smartphone with 1.24B units sold in 2014 out numbering tablets & PC sales.  The expected increase in smartphone application processor (AP) demand in 2015 (Apple A9, Samsung Exynos 7 and Qualcomm Snapdragon) is driving the rapid ramp to 14/16nm 3-D FinFET at foundries, 3-D memory devices such as 128Gb Flash with 32-layers and 3-D stacked chips for package area saving.  Intel was first to production with 3-D bulk-FinFET devices at the 22nm technology node in 2012 and reported their SOC for Chinese low-end smartphones.  Intel’s 2nd generation bulk-FinFET devices at 14nm node was introduced in Aug 2014 and their SOC to follow.  Apple uses Sony’s 8M pixel 3-D stacked backside CMOS image sensor for rear-facing cell phone camera and Samsung offers two versions of the 128Gb Flash memory either 16nm 2-D NAND or 32nm 3-D NAND with 32-layers.  Samsung Galaxy S6 will also use 3-D ePoP (embedded package on package) which stacks AP+DRAM+Flash+MMC saving 40% area and use 20M pixel rear-facing cell phone camera and 8M pixel RWB image sensor for front-facing camera.

To understand 3-D FinFET doping and high mobility channel material, this talk will first review the current doping and Fin/channel mobility enhancement techniques used for 22nm FinFET production by Intel for both high performance logic and SOC devices and the changes they made for their 2nd generation 14nm FinFET.  Apple A6 and A7 used Samsung/Foundry’s 32nm and 28nm technology while the A8 uses TSMC’s 20nm technology.  Later this year, Apple will introduce the A9 which will switch from 2-D planar to 3-D FinFET using both Samsung’s 14nm FinFET and TSMC’s 16nm FF+ technologies. Then at the 10nm or 7nm node higher mobility Fin/channel material (SiGe, Ge or III-V) is expected to be introduced and currently exploratory research of gate-all-around nanowire for 5nm technology node.  Traditional gas/vapor phase epitaxial growth techniques by chemical vapor deposition (CVD) or an alternative liquid phase epitaxial (LPE) regrowth of an amorphous material layer by melt solidification for direct channel mobility enhancement are under investigation.  Finally, a discussion on dopant activation in high mobility material.

PDF of the presentation materials are available here.

Speakers:

John BorlandJohn O. Borland, President, JOB Technologies

John Ogawa Borland received his B.S. and M.S. degrees in Material Science and Engineering from the Massachusetts Institute of Technology (MIT) in Cambridge, MA. He completed his BS thesis research on InP Liquid Phase Epitaxial (LPE) crystal growth at Hughes Malibu Research Labs in 1980 and his MS thesis research on InP Molecular Beam Epitaxial (MBE) crystal growth at Nippon Telephone and Telegraph (NTT) Labs in Musashino, Tokyo, Japan in 1981. He is a senior member of IEEE and the IEEE Hawaii section chair, a member of the Electrochemical Society (ECS) and Materials Research Society. He is co-organizer for the Symposium on ULSI Process Integration IV (2005) and was on the organizing committee for the 2001 & 2003 symposiums, Semiconductor Silicon (1994 & 1998) and Chemical Vapor Deposition X, XI & XII (1987, 1989, & 1991). He also is advisory committee co-chair for the IEEE International Workshop on Junction Technology (2008, 2010, 2011, 2012, 2013 and 2014). He has published over 135 technical and invited papers around the world and has been awarded 6 patents all in the areas of advanced semiconductor device manufacturing techniques. He is also on the Editorial Advisory Board of Solid State Technology magazine.

John was Director of Operations of APIC’s subsidiary Advanced Integrated Photonics which is their Silicon Photonics Foundry Fab in Honolulu, Hawaii from April 2013 to Aug 2014. In June 2003 he founded and is president of JOB Technologies a strategic marketing, sales and technology consulting company providing service to the semiconductor device manufacturing and equipment companies in the area of 14nm down to 7nm node front end of line process development focusing on Ge high mobility material and technology for CMOS.

From July 1998 to May 2003 he was Director of Advanced Business Development at Varian Semiconductor Equipment Associates. While at VSEA, he invented the high tilt high current PoGI process for process simplification and improved device lateral channel and source drain engineering. He also led the revived interest in low temperature diffusion-less activation by solid phase epitaxy (SPE) and its inclusion in the 2003 ITRS roadmap. From Nov. 1992 to July 1998 he was Vice President of Strategic Technology at Genus before they were acquired by Varian and invented the MeV BILLI structure for CMOS epi replacement, process simplification and improved latch-up performance. From Sept. 1983 to Nov. 1992 he was at Applied Materials and pioneering advanced silicon epitaxial and polysilicon/amorphous deposition techniques and equipment designs for blanket epi and polysilicon. He also patented some of his work on selective epi (SEG) and selective poly through surface interface cleaning techniques. This led to the successful implementation of SEG for local strap and elevated source drain by a major DRAM manufacturing company in 1987. Also, a variation to his epitaxial lateral overgrowth (ELO) for SOI is used today for epitaxial bonded SOI wafer manufacturing. From Aug. 1981 to Sept. 1983 he was at National Semiconductor Corp. developing the VHSIC-CMOS front end processing including bulk and epi wafer intrinsic gettering for improved gate oxide integrity and yield as well as substrate and CMOS well engineering for improved latch-up immunity.

Sponsored by Air Products

Air Products has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  www.airproducts.com/advancing

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3D Integration

Date: Thursday, April 23, 2015 at 12:00 p.m. EST

Free to attend

Length: Approximately one hour

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It is well recognized that dimensional scaling has reached its diminishing return phase. The industry is now looking at monolithic 3D to be the future technology driver. Yet, until recently, the path to monolithic 3D has required the development of new transistor types and processes. This Webcast will present game-changing monolithic 3D process flows which use the existing transistor of existing manufacturing line and existing process flows. Now the most effective path for future IC scaling is indeed monolithic 3D, which offers the lowest development and manufacturing cost for future ICs.

PDF of Dr. Vinet’s presentation is available here.

PDF of Mr. Or-Bach’s presentation is available here.

Speakers:

Maud VinetDr. Maud Vinet, Advanced CMOS Manager, CEA/Leti

Dr. Maud Vinet is in charge of the Advanced CMOS Laboratory at CEA Leti in Grenoble, France, a position she has held since 2013. The laboratory pursues conventional scaling through improved electrostatics and transport properties, and also studies alternative paths to conventional scaling either by stacking CMOS over CMOS in a monolithic 3D integration or by adding beyond CMOS devices (Tunnel FET, Single Electron Transistor, nano-mechanical switches) to CMOS to develop a hybrid logic with an optimized cost-energy efficiency trade-off. Maud Vinet has authored or co-authored more than 120 papers (conferences and journals) and owns 40 patents related to nanotechnology.

Zvi Photo DSCN0809 !Zvi Or-Bach, President and CEO of MonolithIC 3D Inc.

Zvi Or-Bach is the founder President and CEO of MonolithIC 3D Inc. Or-Bach has more than 30 years of innovative development including the breakthroughs of monolithic 3D ICs and fast-turn ASICs. Prior to MonolithIC 3D, Or-Bach founded eASIC in 1999 and served as the company’s CEO for six years (eASIC is in process of IPO these days).

Earlier, Or-Bach founded Chip Express in 1989 (recently acquired by Gigoptix) and served as the company’s President and CEO for almost 10 years, bringing the company to $40M revenue. He holds over 150 issued patents, primarily in the field of 3D integrated circuits and semi-custom chip architectures. He is the Chairman of the Board for Zeno Semiconductors, Bioaxial and VisuMenu.

Sponsored by Nordson DAGE

Nordson DAGE is part of the Advanced Technology – Electronics Systems Group of Nordson Corporation (NASDAQ: NDSN) and manufactures and supports a complete range of Industry leading Test and Inspection equipment for the PCBA and Semiconductor industries.  The Nordson DAGE XM8000 Wafer Metrology Platform provides an automated, high-throughput X-ray metrology and defect review system for both optically hidden and visible features of TSVs, 2.5D and 3D IC packages, MEMS and wafer bumps and provides unprecedented, non-destructive, in-line wafer measurement of voiding and fill levels, overlay, critical dimensions. www.measuringtheinvisible.com

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How the IoT is Driving Semiconductor Technology

Date: January 22, 2015 at 1:00 p.m. EST

Free to attend

Length: Approximately one hour

The age of the Internet of Things is upon us, with the expectation that tens of billions of devices will be connected to the internet by 2020. This explosion of devices will make our lives simpler, yet create an array of new challenges and opportunities in the semiconductor industry. At the sensor level, very small, inexpensive, low power devices will be gathering data and communicating with one another and the “cloud.” On the other hand, this will mean huge amounts of small, often unstructured data (such as video) will be rippling through the network and the infrastructure. The need to convert that data into “information” will require a massive investment in data centers and leading edge semiconductor technology.

Click here to register.

Speakers

raitken dac14Robert C. Aitken is an ARM Fellow and heads the Silicon portion of ARM R&D. His areas of responsibility include low power design, library architecture for advanced process nodes, and design for manufacturability. His research interests include design for variability, reliability, and memory design. His group has participated in numerous chip tape-outs, including 6 at or below the 16nm node. He has published over 70 technical papers, on a wide range of topics.  Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP.  He has given tutorials and short courses on several subjects at conferences and universities worldwide. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.

KengeriSubramani Kengeri, Vice President, Global Design Solutions

Subramani is currently the Vice President of Global Design Solutions responsible for world-wide design engineering, semiconductor design eco-system development and design-technology co-optimization. His team enables IP, EDA and SoC solutions in support of “first time right” technology qualification and customer SoC differentiation. He is also responsible for determining technology feasibility, competitiveness and manufacturability of technology platform through design-technology Interactions with customers, technology R&D and design eco-system.

Subramani joined GLOBALFOUNDRIES in 2009 as the Vice President of Design Solutions. He implemented strategic design enablement initiatives and established a strong foundation for collaboration with semiconductor design eco-system. For the last 3 years, as the Head of Advanced Technology Architecture, in the Office of the CTO, Subramani was responsible for defining competitive 14nm, 10nm and 7nm technology platforms. He started his VLSI design engineering career at Texas Instruments and prior to joining GLOBALFOUNDRIES, he was the Senior Director of design and technology platform at TSMC.

Subramani has 25 years semiconductor industry experience and has been granted 38+ U.S. patents. He holds a Master’s degree in electrical engineering from Indian Institute of Technology (IIT, Delhi) and a certificate in executive management from AeA/Stanford University.

Sponsored by Epicor Software Corporation

Epicor Software Corporation is a global leader delivering inspired business software solutions to the manufacturing, distribution, retail and services industries. With over 40 years of experience serving small, midmarket and larger enterprises, Epicor enterprise resource planning (ERP), production control software (MES), and supply chain management (SCM), enable companies to drive increased efficiency and improve profitability. With a history of innovation, industry expertise and passion for excellence, Epicor provides the single point of accountability that local, regional and global businesses demand.

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Trends in Semiconductor Materials

Date: Thursday, November 20, 2014 at 1:00 p.m. EST

Free to attend

Length: Approximately one hour

Chip Level Materials Markets: Growth and Opportunities

Current 3-dimensional structures present new challenges relating to uniformity, lithographic resolution, high aspect ratio etching and fills, and planarization while addressing continuing need to stay at or below current technology node scaling.  What do these challenges really mean in terms of changing material requirements and materials growth opportunities?  In this presentation, Lita Shon-Roy of Techcet will highlight those processes that must have better, alternative process materials, and provide market forecasts on these materials opportunities.

SRC: Exploring Materials Challenges Beyond Moore’s Law

The electronics industry is facing a growing crisis in being able to continue providing cost-effective processes and designs to support the continuation of what’s been referred to as ‘Moore’s Law.’ This ‘Law’, or more accurately ‘observation of the economics involved in scaling integrated circuits,’ has been a very useful guideline for several decades, but as with any similar types of projections, has been expected to some day run its course. While the exact timeframe is still uncertain, that ‘day’ is now within sight, and yet there are still no clear paths forward beyond that point. This presentation will provide a brief glimpse of some of the key materials-related challenges that exist within the frontend (devices), lithography, and backend-of-line (chip level interconnects). It will also include just a few of the research concepts that offer some potential paths forward, which the Semiconductor Research Corporation and its member companies are exploring alongside the university researchers they are supporting.

Click here to register. 

Speakers: 

jon-candelariaJon Candelaria, Director, GRC Interconnect and Packaging Sciences

Jon Candelaria has over 35 years of experience in the electronics industry in a wide variety of engineering and managerial roles. He was most recently a Distinguished Member of the Technical Staff at Motorola’s Applied Research & Technology Center before joining the SRC in September, 2010 as the Director for Interconnect and Packaging Sciences. He has over a dozen issued patents and published technical articles, and received the Motorola Patent of the Year Award for an invention which contributed over $1B to Motorola over the course of its lifetime. He served as Technical Program Chair and General Chair of the IEEE Electron Devices Society’s flagship conference, the IEDM. Jon was the V.P. of Conferences for the IEEE’s Electron Devices Society (EDS), the EDS representative on a joint United Nations-IEEE Humanitarian Challenge advisory committee, and was Chair of both the IEEE Computer Society and Laser and Electro Optics Society Phoenix Chapters. He is currently the Treasurer and Technical Program Committee member for the International Interconnect Technology Conference (IITC), and is a member of the Editorial Panel for Future Fabs International.

litaMugLita Shon‐Roy, President/CEO of Techcet, has worked in the electronics materials industry in business development and technical marketing for more than 25 years. Her work experience spans from business development, marketing and sales of IC’s, equipment, and materials to process development of flat panel displays (TFTs). She has developed new business opportunities for companies such as RASIRC/Matheson Gases and IPEC/Speedfam and helped establish marketing and sales proficiency in companies such as Air Products/Schumacher, Brooktree/Rockwell, and Hughes Aircraft. Lita helped build IPEC as a leader in CMP equipment as Director of International Sales. In 1998, Lita cofounded Techcet Group, LLC. She has authored and co‐authored various articles and texts focused on the semiconductor processing, industry forecasting, and the world economy and is now a recognized expert in electronic materials marketing and business development. Lita holds a Master’s Degree in Electrical Engineering, with a specialty in Solid State Physics from USC and a Bachelor’s Degree in Chemical Engineering from UCSD. She is currently completing her MBA at California State University, Dominguez Hills.

Sponsored by Air Products

Air Products has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  www.airproducts.com/advancing

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Metrology

Date: November 12, 2014 at 12:00 p.m. Eastern

Free to attend

Length: Approximately one hour

The next move in metrology and defectivity for the semiconductor industry

The semiconductor industry today is showing two major trends, as we are approaching the end of the Moore’s Law era.  First, the complexity of the process flow used to make a device has increased extremely fast in recent years.  Second, market demands extend beyond the device to the system, which integrates different functions to achieve a task, leading to 3D integration approaches. The presentation will cover our vision of the consequences of those trends in metrology and defectivity requirements. Carlos Beitia is the Metrology and Defectivity Manager, CEA-Leti, will present: the use of more and more in-lab characterization to complement in-line metrology; the need to combine measurements whether to improve uncertainty in a given parameter or improve knowledge of the object under study; the need for in-die characterization that provides information to complete the picture at transistor and wafer level; 3D integration problems, and more.

Processes for Failure Analysis

Winfield Scott, the Director of Technology at Evans Analytical Group, will present an overview of the failure analysis process as it relates to advanced process technologies will be presented. Layout dimensions are much smaller than the wavelength of light which means transistors cannot be seen with optical microscopes. Many defects appear ‘invisible’ and result in degraded transistor performance instead of opens or shorts. The presentation will include: The failure analysis (FA) methodology and flow; Localizing the failure and identifying the failure site; Localization tools LIVA, TIVA, XIVA, OBIRCH, EMMI, IR, SQUID, LTP; and an example of nanoprobe and TEM.

Click here to register.

Speakers:

wscottWinfield Scott, Technology Director, Evans Analytical Group

Winfield Scott is the Director of Technology at Evans Analytical Group and has the responsibility to ensure EAG has the tools and techniques to keep up with the advances in semiconductors and electronic packaging. He has been using FA to help solve problems for over 40 years. In addition to EAG, he has worked for Motorola, Western Digital, andSperry Flight Systems.

CarlosCarlos Beitia, Metrology and Defectivity Manager, CEA-Leti

Dr. Carlos Beitia received a Ph.D. in material science from Paris 7 University in France. He joined the CEA in 2009 as the scientific manager of the metrology laboratory in Leti’s Silicon Technology Department. Since 2011, he has been the metrology-and-defectivity manager. Previously, he worked for eight years as application engineer at KLA-Tencor focused on advanced metrology applications for worldwide semiconductor fabs. He participates in and leads activities for Leti in several European programs linked to metrology challenges of the semiconductor industry (SEA4KETs, Master 3D, Polis). He is member of the ITRS metrology working group and theFrench Nanometrology Club. His actual field of research is in metrology in optical profilometry and AFM for surface nanotopography and surface functionalization.

About the sponsor: 

Bruker Nano Surfaces is the world’s leading supplier of probe based metrology & failure characterization systems supporting the semiconductor industry with fully automated Atomic Force Microscopes and AFM probes designed specifically to address CD, depth and CMP metrology in a production environment. Come see how Bruker’s unique PeakForce Tapping capability for FinFETs, 3D-NAND and EUV lithography can help solve your critical process problems by providing unparalleled accuracy and precision. Find out more at www.bruker.com/afm.

Advanced Packaging


May 12, 2014

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Advanced Packaging

Date: October 16, 2014 at 1 p.m. EST

Free to attend

Length: Approximately one hour

Speakers: Ramakanth Alapati, Senior Manager, Package Architecture and Customer Technology Group, GLOBALFOUNDRIES and Devan Iyer, Director of SC Packaging at Texas Instruments

Click here to register.

Back-end packaging is increasingly important to semiconductor device form factor, thermal and power performance, and costs. Compounded by the demand for lead-free processing and the soaring cost of gold, the industry is developing new approaches to packaging, including redistribution layers (RDL), through silicon vias (TSV), copper pillars, wafer-level packaging (WLP) and copper wire bonding. Experts will discuss these and other approaches in this webcast.

Speakers:

Rama AlapatiRamakanth Alapati, Senior Manager, Package Architecture and Customer Technology Group, GLOBALFOUNDRIES, will discuss the increasing complexity of chip-package interactions (CPI) due to expanding package options at leading edge nodes. He will discuss how foundries need to plan for qualifying multiple BEOL Stack options with the multitude of package options that customers have. He will also discuss the IO density scaling options and relative costs of each of the package types and challenges in die stacking for 2.5D technologies.

Iyer_Devan_11-20-12Devan Iyer, Director of SC Packaging at Texas Instruments will talk about why the use of copper wire bonding in semiconductor packages has seen a steady evolution in recent years. The technology offers better performance and is more economical than traditional gold wire bonding, and Texas Instruments has played an instrumental role in developing copper wire bonding across the industry. Devan will talk about the benefits of this copper wire bonding to many applications, even the extension to high-reliability auto and industrial applications.

Sponsored by EV Group and Zeta Instruments

EV Group, Inc. (EVG) is a leading supplier of processing equipment and process solutions for the manufacture of semiconductor components, microelectromechanical systems (MEMS), compound semiconductor, power and nanotechnology devices.  Key products include wafer bonding, thin-wafer processing, lithography / nanoimprint lithography (NIL) and metrology equipment as well as photo-resist coaters / developers, and wafer inspection systems.  Founded in 1980, EVG services and supports a varied network of global customers and partners all over the world.  More information about EVG is available at www.EVGroup.com.

Zeta Instruments is a dynamic start-up company based in Silicon Valley that specializes in wafer defect inspection and metrology instruments. We combine our innovative optics design with advanced software algorithms in products tailored for the target applications in the semiconductor and adjacent markets. In addition to innovative technologies, Zeta Instruments is focused on delivering best-in-class hardware and very user-friendly interfaces. For further details, please contact Zeta Instruments at : www.zeta-inst.com

August 14th at 1:00 p.m. ET

Wet Processing, including wafer cleaning, is one of the most common yet most critical processing step, since it can have a huge impact on the success of the subsequent process step. Not only does it involve the removal of organic and metal contaminants, but it must leave the surface in a desired state (hydrophilic or hydrophobic, for example), with minimal roughness and minimal surface loss – all on a growing list of different types of materials. In this webcast, experts will identify industry challenges and possible solutions, including a new concept of tailoring chemistries to dissolve very small particles rather than physically removing them.

Register here: https://event.webcasts.com/starthere.jsp?ei=1040703

Speakers:

Reidy_R-cropDr. Rick Reidy is a professor in the Department of Materials Science and Engineering at the University of North Texas (UNT). He is a member of the SEMATECH Surface Preparation and Cleaning Conference, Organizing Committee, the International Technology Roadmap for Semiconductors (ITRS) Front End Processes- Surface Preparation Technical Working Group and a co-chair of the Interconnect Surface Preparation Focus Team. Dr. Reidy’s research interests are supercritical processing of semiconductor materials, synthesis and characterization of novel porous ceramics for dielectric, sensor and energy applications, and ultra-low k dielectrics.

Abbas Rastegar_SEMATECH[2]Dr. Abbas Rastegar, is a Fellow in Technical Strategy Group at SEMATECH.  Abbas joined SEMATECH in 2003 where he managed cleans program in the Lithography. Since 2013, he managed  R&D in nanodefectivity in SEMATECH. Abbas has about 25 years of R&D experience in different physics, macromolecules, nano-science, and nano-technology disciplines with more than 150 published papers in technical journals and conferences.

 

Sponsored By

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SSEC

Veeco Instruments Inc. today introduced the Apex Gas Mixing System for point-of-use gas mixing. The Apex system generates precise binary gas mixtures on a single platform for use in semiconductor applications at 20nm and below.

The Apex Gas Mixing System improves concentration control versus existing methods, providing tighter process management, increased tool uptime and reduced manufacturing costs. It is optimized for advanced silicon epitaxy applications and other processes requiring low concentration, high precision and cost sensitive gas mixtures.

“Our new Apex Gas Mixing System addresses key challenges that face semiconductor manufacturers at the 20nm node and below,” said Christopher Morath, Senior Director, Veeco Flow Technologies Group. “For example, the Apex system provides precise control of germane and diborane flux for doped silicon germanium films that have a critical impact on device performance with tight process control limits. Consequently, the Apex system allows manufacturers to improve real-time process control by up to a factor of ten as compared to mixed gas cylinders. This will enable users to increase both yield and throughput.”

The Apex system, powered by Veeco’s production-proven Piezocon® Gas Concentration Sensor, reduces production costs by allowing manufacturers to purchase lower-cost, higher-concentration gases, then dilute them at the point of use to immediately cut gas purchase costs by as much as 60 percent. The Piezocon Gas Concentration Sensor total installed base is over 3,000 sensors worldwide, in both silicon semiconductor and MOCVD applications.

By using the Piezocon Gas Concentration Sensor to measure and control the mixture in real time, manufacturers eliminate the problems associated with constant flow mixers requiring wasted materials and constant scrubbing, adding to the already substantial cost savings. Using the Apex Gas Mixing System provides stable output and precise control of gas concentration, resulting in higher process tool up-time and eliminating the need to re- qualify after every gas cylinder change. These improvements reduce – and in some cases eliminate – system down-time due to routine cylinder changes. These features allow the Apex system to drive real-time control, high precision and reproducibility and lower cost of ownership for semiconductor manufacturers.