Category Archives: Uncategorized

June 19, 2014 at 12:00 p.m. EST

Although Micro-Electro-Mechanical Systems (MEMS) have been around for a long time, the introduction of the technology into consumer markets, with Nintendo’s Wii in late 2006, opened the floodgates with multiple MEMS – accelerometers, gyros, compasses, pressure sensors and microphones — now in smartphones and tablets. And you ain’t seen nothing, yet!

Register here: https://event.webcasts.com/starthere.jsp?ei=1037134

Jay-face-shotPresenter: Jay Esfandyari, Director of MEMS and Analog Product Marketing at STMicroelectronics

 

 

SimoneSeveri

Presenter: Simone Severi, lead for SiGe MEMS at imec

SiGe MEMS technology for monolithic integration on CMOS

Recent development of MEMS technologies at IMEC enables the monolithic integration of MEMS on CMOS. This approach represents a potential key advantage for a variety of MEMS systems as it can lead to a device performance improvement and to the scaling of the system area with consequent cost and package size reduction. Systems requiring multiple MEMS devices on chip or large MEMS array will benefit the most out of this approach.

One route focuses on the direct post processing on top of CMOS of a low temperature SiGe material, fully compatible with standard Al back end of line processes. This platform can realize a compact system for multi sensing applications. Accelerometers, capacitive pressure, compass and temperature sensors are among the candidate sensors to be combined on the same chip, e.g., to yield implantable (or wearable) products for the medical field, chips for the consumer or automotive market. Array of Capacitive Micromachined Ultrasonic Transducers are demonstrated for potential medical imaging systems. Key asset for the success of this CMOS-MEMS monolithic approach is the implementation of an hermetic thin film packaging technology. Thin film hermetic SiGe packages are demonstrated with cavity pressure ranging from few Pa up to several 100mBar. This technology has the potential to enable a scaling of the form factors while reducing packaging and testing costs.

Sponsored by:

SSEC

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Samsung Electronics said today that it has begun mass producing the industry’s first high-performance, three-bit-NAND-based SSD for servers and data centers. The new SSD will allow data centers to better manage workloads related to social networking, web browsing and email, and enhance operation efficiency. Installations of the 3-bit MLC (multi-level-cell) NAND SSDs, initially in large-scale data centers, are expected to begin later this quarter.

“Following the last year’s introduction of 3-bit NAND-based SSDs for PC markets, our new 3-bit SSD for data centers will help considerably in expanding the market base for SSDs,” said Young-Hyun Jun, executive vice president, memory sales and marketing, Samsung Electronics. “We expect SSD market growth will gain momentum as this new SSD delivers significant improvements in data center investment efficiency, leading to full-fledged commercialization of SSDs in IT systems later this year.”

The new PM853T SSD, available in densities of 240GB, 480GB and 960GB, offers high levels of random IOPS (inputs/output per second) performance and quality of service (QoS), both essential for data center and cloud server applications. In light of these benefits, Samsung expects the adoption of 3-bit SSDs in data centers to advance rapidly in replacing the 2-bit SSD market.

In broadening the market base for SSDs, the new PM853T SSD will enable IT managers to optimize their SSD upgrades at investment levels similar to those of consumer SSDs. The PM853T delivers a 30 percent increase in manufacturing efficiency compared to SSDs that use 2-bit NAND flash components.

Utilizing Samsung’s 10nm-class 3-bit NAND flash components and advanced controller technology, the new drive features a sequential read speed of 530 megabytes per second (MB/s), while writing sequentially at 420MB/s. It also will read data randomly at 90,000 IOPS and handle sustained random writes at 14,000 IOPS.

Since it first produced the 3-bit NAND-based 840 EVO SSD in 2012, Samsung has taken the lead in providing SSDs for ultra-slim notebooks and PCs. With the PM853T, it has now secured a strong foothold for high-efficiency SSDs in large data centers.

Through this introduction of a SATA 6Gb/s 3-bit SSD, Samsung is reinforcing its collaboration with global data center and server customers, while continuing to offer the broadest line up of competitive SSDs (spanning SATA, SAS, and PCIe/NVMe interfaces) to increase its leadership position in the premium SSD market.

According to a market research report from IHS iSuppli, the global SSD market is expected to grow approximately 30 percent from U.S. $9.4 billion in 2013 to U.S. $12.4 billion in 2014. The report says it will also maintain a high growth rate over the next several years, reaching up to U.S. $20 billion in 2017.

Verity Instruments, Inc. is pleased to announce the availability of its new SP2100 Spectral Reflectometer designed for film thickness measurement for in-situ and in-line applications.

The SP2100 consists of a high performance spectrometer and Xenon flashlamp with a number of unique features.  These include a two-dimensional, thermoelectrically cooled CCD array that enables the system to simultaneously monitor one to six fiber optic inputs allowing uniformity measurements of up to six points on the same substrate. The integrated Xenon flashlamp provides high intensity, wide spectral range illumination with the ability to separate contaminating background light using an alternating flashlamp mode, along with the ability to provide unblurred measurements in the case of a moving substrate.

The SP2100 is supplied with Verity’s proprietary SpectraView application software that includes various model based and fringe counting thin film measurement algorithms. System integration is possible using RS232 (serial or protocol- based), Ethernet, or Digital I/O communication, and a variety of optical collimators are available for tool integration.

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Kimberly-Clark Professional has introduced a new glove that is designed to provide process protection for the semiconductor and electronics industries.

Kimtech Pure G3 EvT Nitrile Gloves offer high performance, durability and value. Free of natural rubber latex, these Extra-Value Technology gloves are preferred by cleanroom operators for overall tactile performance. They also offer:

·      Superior comfort
·      Easy donning
·      Enhanced grip

“These gloves offer peace of mind in industries where a single spec of dust on a worker’s glove can ruin a $10,000 wafer,” said Carolina Krevolin, category manager, Scientific Gloves, Kimberly-Clark Professional. “Plus they deliver cleanliness, value and sustainability.”

Kimtech Pure G3 EvT Nitrile Gloves are recyclable through the RightCycle by Kimberly-Clark Professional program – the first large-scale recycling program for non-hazardous laboratory waste. They also save space and reduce waste via environmentally responsible packaging that results in 50 percent more gloves per case (providing 33 percent more storage space) and 34 percent less waste.

Kimberly-Clark Professional is a provider of contamination control solutions for cleanrooms and laboratories. Through the RightCycle Program, the business has helped divert 130,000 pounds of disposable garments and 30,000 pounds of nitrile gloves from landfills.

kimtech gloves

UVOTECH Systems, Inc., a manufacturer and distributor of surface treatment equipment, announced the release of a new UV-Ozone Cleaning System, Model HELIOS-500. This is the first product in the HELIOS series of UV-Ozone Cleaners by UVOTECH.

Helios-500

The HELIOS-500 system is designed to be very compact, lightweight and economical. It includes an ultraviolet grid lamp for increased uniformity as well as a digital process timer which allows more accurate control over the process time. The drawer loading sample stage can accommodate up to 5”x5” substrates. Included pedestals allow for adjusting the distance between the UV source and substrate. This system also comes with a built-in hour-counter which will record the total hours of the UV lamp usage for maintenance purposes.

The UV Ozone Cleaning process is a photo-sensitized oxidation process in which the contaminant molecules of photo resists, resins, human skin oil, cleaning solvent residues, silicone oils, and flux are excited and/or dissociated by the absorption of short wavelength UV radiation. Atomic oxygen is simultaneously generated when molecular oxygen is dissociated by 185nm and ozone by 254nm ultraviolet wavelengths. The 254nm UV radiation is absorbed by most hydrocarbons and also by ozone. The products of this excitation of contaminant molecules react with atomic oxygen to form simpler, volatile molecules, which desorbs from the surface. Therefore, when both UV wavelengths are present atomic oxygen is continuously generated, and ozone is continually formed and destroyed.

Using a UV-Ozone Cleaner, near atomically clean surfaces can be achieved in minutes without any damage to your devices. This fast method of obtaining ultra-clean surfaces free of organic contaminants on most substrates, such as quartz, silicon, gold, nickel, aluminum, gallium arsenide, alumina, glass slides, etc. can easily be achieved by utilizing a UV-Ozone Cleaner in just a few minutes.

March 27th 1:00 p.m. ET

Register here: https://event.webcasts.com/starthere.jsp?ei=1032084

2.5/3D integration and advanced packaging enable better chip performance in a smaller form factor, meeting the needs of smartphones, tablets, and other advanced devices. However, 2.5/3D packaging creates a new set of manufacturing challenges, such as the need to fabricate copper pillars, TSVs, wafer bumping and redistribution layers – which may involve thicker photoresists, spin-on dielectrics and BCB coatings — and processing may be done on panels instead of round wafers. In this webcast, experts will detail various options, future scenarios and challenges that must still be overcome.

Speakers:

SitaramSitaram Arkalgud

Sitaram Arkalgud is Vice President, 3D technology at Invensas Corp., where he leads the company’s 3D-IC research and development efforts. Prior to Invensas, he started and led 3D-IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for 3D interconnects. Previously, Sitaram worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. He is the author of several publications and holds 14 U.S. patents. Sitaram holds a master’s degree and a Ph.D. in materials engineering from Rensselaer Polytechnic Institute in Troy, N.Y., and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College, Surathkal, India.

rogoff-richRichard Rogoff

Richard Rogoff is Vice President and General Manager of the Lithography Systems Group at Rudolph Technologies. Prior to joining Rudolph he spent 23 years with ASML in various executive, operational and engineering positions. Most recently he served as Vice President of ASML optics business unit. He received a B.S. in Microelectronic Engineering from Rochester Institute of Technology and a M.B.A. from INSEAD Business School.

 

Sponsored by:

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Rudolph Technologies, Inc. is a worldwide leader in the design, development, manufacture and support of defect inspection, advanced packaging lithography, process control metrology, and data analysis systems and software used by semiconductor device manufacturers worldwide. Rudolph provides a full-fab solution through its families of proprietary products that provide critical yield-enhancing information, enabling microelectronic device manufacturers to drive down the costs and time to market of their products. the Company’s expanding portfolio of equipment and software solutions is used in both the wafer processing and final manufacturing of ICs, and in adjacent markets such as FPD, LED and Solar. Headquartered in Flanders, New Jersey, Rudolph supports its customers with a worldwide sales and service organization.

NanoWorld AG announced the official commercialization of six types of Ultra-Short Cantilevers (USC) dedicated for use in High-Speed Atomic Force Microscopy (HS-AFM).

High Speed Atomic Force Microscopy is a quickly evolving technique within the field of Scanning Probe Microscopy that enables the users of dedicated instruments and AFM probes to visualize dynamic processes at the single molecule level.

After a very successful beta-testing phase, six types of AFM probes for high speed scanning will be commercially available from now on.

In order to provide a suitable probe for the complete range of high speed scanning applications, the Ultra-Short Cantilevers series consist of six different types of AFM probes divided in 2 categories.

Three types of Ultra-Short Cantilevers with very high resonance frequencies (1.2 MHz – 5 MHz) and high force constants are mainly meant for use in dynamic mode applications in air.

All AFM probes of the USC type feature a wear resistant  tip made from High Density Carbon/Diamond Like Carbon (HDC/DLC) with a typical tip height of 2.5 µm and a radius of curvature typically < 10 nm. The aspect ratio is typically 5:1 and the tilt compensation is 8°.

The cantilevers are coated with gold on both sides but the tip remains uncoated.

Electrolube, a supplier of formulated chemical products to the global electronic, industrial and domestic devices manufacturing sectors, will be launching a versatile new silver conductive adhesive at APEX Expo 2014 in Las Vegas (March 25-27). The product will be of particular interest to designers and manufacturers of liquid crystal displays (LCDs) and liquid crystal monitors (LCMs) who seek to improve the efficiency of their manufacturing processes.

Dubbed SCPH, this new silver conductive adhesive is suitable for the assembly of cellphone display modules, tablets and similar products that incorporate flat screen displays. It offers excellent electrical conductivity and good adhesion to most substrates, especially indium tin oxide and colour filter substrates.

Significantly, SCPH is not dissolved by Tuffy conformal coatings, which are frequently applied to the electrodes of flat panel displays. This means that it can be coated with Tuffy alternately, which greatly simplifies the assembly process and results in marked improvements to production efficiency.

SCPH is suitable for use with fast-action, automatic dispensing equipment and will cure at ambient temperatures within ten minutes. It is halogen and antimony free, and requires no special storage conditions.

Recently launched in China, where it has met with considerable success among manufacturers of touchscreen products, SCPH silver conductive adhesive will be unveiled next to US audiences at APEX Expo (booth 2119), Las Vegas, March 25-27 2014 and the Design-2-Part show on May 7-8 in Schaumburg, Illinois.

Park Systems, a manufacturer of Atomic Force Microscopy systems since 1997 announced PinPoint Conductive AFM, an extremely accurate conductive measurement technology at nano-scale resolution for failure analysis (FA) in the semiconductor industry. The newly designed and innovative Park Systems PinPoint iAFM effectively solves the issues of traditional AFM thereby providing the most optimum solution to the FA engineers’ needs available in the nanotechnology industry today.

“Conductive AFM is an important tool for device research and failure analysis and with the introduction of PinPoint Conductive technology, Park Systems has succeeded in solving all of the shortcomings of conventional conductivity AFM such as quick tip wear, degradation of resolution, low signal to noise ratio, no tip pressure control, and poor reproducibility of data.  The conventional conductive AFM prevalent in the industry has to sacrifice the spatial resolution as the tip wears out in contact mode or the current level due to short and limited contact time,” explains Ryan Yoo, Vice President of Global Sales and Marketing.  “The newly developed PinPoint Conductive AFM provides the best of both higher spatial resolution and optimized current measurement.”

The advantages offered by PinPoint iAFM are of utmost importance because they can overcome and often eliminate the respective difficulties that are present in the conventional Conductive AFM and solve the respective FA problems faced by engineers with respect to SRAM (static random access memory) cells.  The Pinpoint AFM technique offers the lowest current noise level (< 0.1 pA), the maximum current available in the industry (10 mA) and the highest gain selection in the industry (it covers approximately seven orders of magnitude (106 – 1012).  Furthermore, the controllable data acquisition time allows for a very high signal-to-noise ratio.Park’s PinPoint AFM is therefore an extremely effective tool for the characterization of electrical defects in SRAM cells for failure analysis.

By using Park Systems PinPoint Conductive AFM, scientists and engineers can acquire contact current measurement at any specific location of a sample at varying tip pressures, and at a much higher accuracy and precision than what has been possible to-date.  Added benefits from this technology are frictionless conductivity scanning, reproducible data from repeated measurements, cost savings from longer lasting AFM probe tips, and sustained super high nano-resolution.  Park’s new PinPoint Conductive technology provides on-location electrical conductivity data at specific points on sample to researchers and failure analysis engineers and offers frictionless conductivity scanning and excellent high spatial resolution and sensitivity with a very high signal-to-noise ratio.

In PinPoint Conductive mode, the AFM probe monitors its feedback signal, approaches towardsthe sample surface until a predefined threshold point, measures the Z scanner’s height, then it rapidly retracts. The XY scanner stops during the electric current acquisition, and the contact time is controlled to assure enoughtime for quality data acquisition. PinPoint Conductive AFM allows higher spatial resolution with optimized current measurement over different sample surface; furthermore, it does not apply any lateral force thanks to the decoupled vertical movement of the Z scanner of the cantilever.

PinPoint Conductive was designed to replace the conventional contact conductive AFMand is an enhanced design that eliminates the problems of the tip wearing out during contact mode topography and diminished contact time.  Park’s PinPoint Conductive AFM enables engineers and research scientists to characterize and confirm electrical designs of semiconductor device structures with much more accuracy, precision and confidence in the data.

The need for high sigma yield


February 24, 2014

By Dr. Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Inc.

In the mid-1990s, the former head of General Electric Jack Welch and Six Sigma were all but synonymous. Many a corporation implemented Six Sigma to improve process quality, based on Welch’s outspoken endorsement of the program.

Today, the semiconductor industry is using similar terminology to refer to high sigma yield prediction, a means to statistically determine the impact of process variations on parametric yield for integrated circuits such as SRAM that require extremely low failure rate.

No one needs to be Jack Welch to know why. In fact, it’s a huge challenge for the industry and it has been getting the attention it deserves of late –– the move to state-of-the-art 28nm/20nm planar CMOS and 16nm FinFET technologies present greater challenges to yield than any previous generation.

The key challenge is high sigma yield analysis that covers yield from roughly the 4 to 7+ σ range –– the range where traditional Monte Carlo simulation methods break down due to the requirement of high-sample numbers with associated long run times. For 3 σ designs, Monte Carlo continues to be a viable solution.

Foundries now require SRAM memory verification to 7 σ in 16nm FinFET technology, a technical impossibility without deploying a special high sigma yield prediction tool. The reason memory bit cell yield targets are being set so high is due to large process variations and shrinking design margins at advanced nodes and larger memory sizes. Most commercially available tools are unable to address 7+σ reliably or accurately.

Multiple methods are available to tackle the high sigma challenge, discussed at length in a recent ProPlus whitepaper. The key is an accurate and reliable estimate of yield out to very high sigma values with a reasonable number of simulations.

High Sigma methods that utilize Monte Carlo as the foundation are able to take advantage of its robustness but overcome its inability to scale to high sigma analysis. Designers are further pushing the high sigma boundary running the analysis on larger and larger blocks, such as an SRAM array. The requirement to analyze large designs with tens of thousands of variables creates a compounding effect on the high sigma problem.

This gives a glimpse into the scope of the high sigma challenge. On the one hand, there is a need to validate yield out to 7+ σ ranges. On the other, there is pressure to run high sigma analysis on large designs.

Yes, challenges abound. More than one industry expert is calling for an integrated design for yield (DFY) flow to answer the challenge. That’s because the conventional design flow is outmoded and struggling under the weight of these weighty requirements. An integrated DFY flow, advise the experts, needs accurate statistical device modeling and a powerful SPICE simulator. Most important, the new flow needs yield prediction, analysis and fixing capabilities that can cover requirements from 3 to 7+ σ yield.

Few tool providers today offer all three in an integrated DFY flow. In fact, most electronic design automation (EDA) tool providers in this space offer one product that may or may not be “best in class.” While “best in class” may suggest a company focused on its core competence, it’s a mistake to think that not providing an integrated DFY flow is an acceptable practice in the era of FinFET.

Anyone in charge of developing or managing a complete DFY flow should employ the principals of Six Sigma consistently through all three stages of the whole flow. The checklist should start with an integrated DFY methodology that neatly packages statistical device modeling and a powerful SPICE simulator with yield prediction, analysis and fixing capabilities up to and beyond 7 σ.  A designer should be able to tick off on the checklist the key points of accuracy, productivity improvement, scalability, high s yield, high σ optimization, and cost effectiveness.  That’s the recommendation for EDA teams and designers in the FinFET era. And, one that Jack Welch would endorse.