Category Archives: Uncategorized

SPTS Technologies and imec announced a joint partnership to further advance micro- and nanosized components for BioMEMS, using SPTS’ Rapier silicon deep reactive ion etching (Si DRIE) technology.

Micro and nanotechnologies are fast becoming key enablers in medical research, diagnosis and treatment, with rapid developments in areas like DNA sequencing and molecular diagnostics. Imec, as one of the pioneers in the field, is developing the underlying heterogeneous technology and components as the backbone to these life science tools.

One of the most important process techniques in BioMEMS manufacturing is deep silicon etching. It can be used to manufacture devices such as microfluidic channels, polymerase chain reaction (PCR) chambers, mixers and filters. As a leading institute in advanced micro and nanoelectronics research, imec is currently developing lab-on-chip technology for fast SNP (single nucleotide polymorphisms) detection in human DNA and a microsized detection system for circulating tumor cells in the human blood stream. The outcome of this research will be products that deliver a better quality of life for current and future generations.

IMEC_NR_SPTS

“We chose SPTS as a partner after running extensive wafer demonstrations on their tool, challenging them on the demanding structures required by our current projects,” says Deniz Sabuncuoglu Tezcan, who is leading imec’s Novel Components Integration team. “The results convinced us that the Rapier module can help us create the devices we envisage. The demos also showed that the processes will deliver the high throughputs and repeatability necessary for cost-effective volume production.”

Brooks Instrument, a provider of advanced flow, pressure, vacuum and level solutions, has expanded its GF 40/80 Series portfolio of thermal mass flow controllers (MFCs) to enable a broader range of applications.

The new GF81 MFC can be used for gas flow rates up to 300 slpm, making it ideal for high-flow applications in thin film, solar, analytical, biotech and fuel cell.

The GF81 provides the same high-stability sensor and best-in-class repeatability as the GF40/80 Series, but with a higher flow rate. Compared with competitive products offering a similar flow rate, the compact footprint and low power draw of the GF81 allows users to design smaller, more efficient systems. It also provides better actual process gas accuracy over devices that use traditional single-point conversion factors.

The GF81 Series features an all-metal seal flow path for durability and high leak integrity, precise flow control with fast sub-1-second settling times, and 1% of reading accuracy to ensure reliable flow measurement and control in demanding gas flow applications. A wide range of digital and analog I/O options offers the broadest range of communication protocols, making the GF81 an ideal upgrade for existing MFCs or MFMs.

Brooks

The dry pumps A 100 L with their compact dimensions were specially developed for flexible integration in semiconductor production facilities. These dry multi-stage Roots pumps are ideal for clean applications such as load-lock chambers and transfer chambers as well as for all other noncorrosive applications.

Despite their compact dimensions these pumps provide high pumping speeds and short pump down times. Today, the A 100 L pumps are installed worldwide in all leading semiconductor fabs. These pumps are suitable for operation in cleanrooms.

The further development, the A 100 L ES, cuts energy consumption by  up to 50% (ES = Energy Saving). Its pumping speed is significantly higher in the low pressure range. Additional benefits include a lower final pressure and reduced noise level.

The innovative and fully integrated ES module reduces energy use to a minimum in the low pressure range. This significantly reduces operating costs. To illustrate the point: annual savings per pump total up to 7,900 kWh. This corresponds to 3.9 tons of CO2.

At a typical 300 mm semiconductor fab level equipped with 1,300 load-lock pumps, the energy saving adds up to 10 GWh, or about 360 k€ or 5,100 tons of CO2 per year.

In addition to energy savings, the final pressure of the A 100 L ES is reduced to 7×10-4 mbar (hPa). This opens up new potential applications requiring an enhanced pumping capacity combined with low pressure. The noise level is also reduced from 58 dB (A) to 55 dB (A). The A 100 L ES rounds off the energy-saving product family of medium duty process pumps in the A3P series and the harsh duty process pumps in the A3H series.

ProductLarge14698

At the International Electron Devices Meeting (IEDM) in December, IBM researchers will describe a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured a 30nm SiNW pitch with a gate pitch of 60 nm.

Devices with a 90nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100 nm— peak/saturation current of 400/976 µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.

IBM F2

The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.

The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.

A new two-step anneal process shows that the nanowires can be smoothened with no loss of density compared to planar processes.

A new two-step anneal process shows that the nanowires can be smoothened with no loss of density compared to planar processes.

The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts; (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).

The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts; (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).

 

 

 

At the International Electron Devices Meeting (IEDM) in December, TSMC researchers will unveil a 16nm FinFET process that by many measures is one of the world’s most advanced semiconductor technologies.

 

In size, it is the first integrated technology platform to be announced below the 20 nm node, with key features including a 48-nm fin  pitch and the smallest SRAM ever incorporated into an integrated process—a 128-Mb SRAM measuring 0.07 µm2 per bit. In performance, it demonstrated either a 35% speed gain or a 55% power reduction over TSMC’s existing 28-nm high-k/metal gate planar process, itself a highly advanced technology, and had twice the transistor density.  Short-channel effects were well-controlled, with DIBL <30 mV/V, saturation current of 520/525 µA/µm at 0.75V (NMOS and PMOS, respectively) and off-current of 30 pA/µm. It incorporates seven levels of high-density copper/low k interconnect and high-density planar MIM devices for noise control.

Figure 1 shows that the 16 nm FinFET achieved either a >35% speed gain or >55% power reduction over TSMC’s planar process.

Figure 1 shows that the 16 nm FinFET achieved either a >35% speed gain or >55% power reduction over TSMC’s planar process.

 

Figure 2 shows a cross-section of the device’s 7-level metal copper/low-k architecture.

Figure 2 shows a cross-section of the device’s 7-level metal copper/low-k architecture.

 

SPICEing up circuit design


September 25, 2013

Dr. Zhihong Liu

Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, blogs about the challenges of designing for yield using SPICE models. 

The ubiquitous SPICE circuit simulator, initially released 40 years ago, made a recent list of the top 10 most significant developments in the history of EDA, as it should. Its widespread use and importance among circuit designers cannot be understated.

However, the third-generation of SPICE (Simulation Program with Integrated Circuit Emphasis) simulation is showing its age. Circuit designers are doing giga-scale simulations because of complex designs, increasingly simulated post-layout and the large number of simulations required to design for variation effects.

Giga-scale designs range from post-layout analog circuits, high-speed I/Os, memory and CMOS image sensor arrays to full-chip power ICs, and clock trees and critical path nets. They require a parallel SPICE simulator with high capacity in the order of tens of millions of elements for analog designs and hundreds of million elements for memory designs. A SPICE simulator needs to deliver high performance with pure SPICE accuracy and offer support for the latest process technologies such as FinFETs.

Three dimensional FinFETs bring additional challenges to device modeling and circuit simulations. Modeling and simulation tools must be able to handle increased layout dependencies in device characteristics and more complex parasitics, including internal parasitics and interactions between the device and surrounding components.

Current SPICE simulators can offer few of these must haves. Traditional SPICE simulators lack capacity even with parallelization capabilities. FastSPICE simulators deliver capacity at the cost of accuracy and are losing steam as an increasing number of designs require post-layout verification that weakens circuit hierarchy. The FastSPICE table model approach and approximated matrix solutions can offer unreliable results and poor usability for complicated giga-scale designs with multiple operating modes and supply voltages.

The key is to maintain simulation accuracy as traditional SPICE simulators do, and simultaneously, be able to handle large circuit simulation capacity that typically only FastSPICE simulators can do with reasonable simulation time. In today’s bleeding-edge designs, designers often can’t settle for performance or capacity by sacrificing accuracy as FastSPICE simulators can.

EDA vendors are aware of these trends and the increasingly urgent market needs. Almost all existing SPICE and FastSPICE simulators have been working hard to utilize parallel technologies on multicore and/or multi-CPU computing environments to improve simulation performance. However, patched-on parallelization offers short-term improvement, and can’t fully meet the need for simulation accuracy, performance and memory consumption for giga-scale circuit designs.

New simulation technology is essential for deep-nanometer technology designs where process variations impact circuit yield and performance. In addition to capacity challenges related to increasing circuit size, designers need to run large numbers of repeated simulations to tackle the impact of process variations. Process-Voltage-Temperature (PVT) analysis and statistical Monte Carlo analysis create another challenge dimension for giga-scale simulations.

In a circuit designer’s ideal world, the next-generation SPICE circuit simulator would be highly accurate with full SPICE analysis features and support for industry-standard inputs and outputs. It would be much, much faster than traditional SPICE simulators and able to handle all circuit types. The ability to simulate giga-scale circuits and challenging post-layout designs is mandatory. Building parallelization in a SPICE simulator from the ground up instead of patched-on solutions is the key to handling giga-scale simulations with good performance and memory consumption, while still offering SPICE accuracy. Most aging circuit simulators will soon show their limitations.

Ideally, the new SPICE simulator also will have native capabilities to handle process variations from 3-sigma to high-sigma Monte Carlo simulations, where hundreds or even thousands of simulations are needed. Circuit designers have begun to search for Design-for-Yield (DFY) solutions and not just cobbled-together point tools. A total DFY solution starts with a high-capacity, high-performance SPICE simulator as its engine. A simulator designed for DFY with built-in statistical simulation capabilities can provide incomparable simulation performance when compared to ad-hoc variation analysis with external circuit simulators.

And, of course, the SPICE simulation engine should be tightly integrated with statistical transistor model extraction and yield prediction/improvement software. Those components make a total DFY solution, and enable the efficiency and consistency of yield-analysis results.

Giga-scale simulation isn’t the future, it’s here today and needs viable solutions to meet the challenges it has created. SPICE simulators have served the circuit design industry for 40 years, and it’s time for the next generation, essential for deep nanometer technology designs.

PC outlook lowered again


August 30, 2013

Worldwide PC shipments are now expected to fall by -9.7 percent in 2013, further deepening what is already the longest market contraction on record, according to the International Data Corporation (IDC) Worldwide Quarterly PC Tracker. The new forecast reflects not only a continued expansion of mobile device options at the expense of PCs, but also marked the cessation of emerging market growth that the industry had come to rely on in recent years. The market as a whole is expected to decline through at least 2014, with only single-digit modest growth from 2015 onward, and never regain the peak volumes last seen in 2011.

While the results of the second quarter were in line with forecast, a number of issues led IDC to further downgrade its PC outlook. Aside from stubbornly depressed consumer interest, 2013 also marks the first year where emerging regions are expected to contract at a steeper rate than mature regions. Leading this trend is China’s revised forecast, which calls for a double-digit decline in shipments this year compared to 2012, as channel sources report high levels of stagnant inventory and continued enthusiasm for tablets and smartphones. The repercussions of a slowing China, anxiety over the possible tapering of the U.S. quantitative easing program, and weak intrinsic PC demand are among a litany of factors that have rippled across portions of other formerly strong-growth areas, leading emerging markets as a whole to see declines through at least 2014.

“The days where one can assume tablet disruptions are purely a First World problem are over,” said Jay Chou, senior research analyst, Worldwide Quarterly PC Trackers at IDC. “Advances in PC hardware, such as improvements in the power efficiency of x86 processors remain encouraging, and Windows 8.1 is also expected to address a number of well-documented concerns. However, the current PC usage experience falls short of meeting changing usage patterns that are spreading through all regions, especially as tablet price and performance become ever more attractive.”

Looking beyond 2014, IDC expects a slow rebound, driven in part by modest consumer refresh of systems whose lifecycle have dramatically lengthened in recent years, as well as businesses taking a first serious look beyond Windows 7. However, without an adequate mass of compelling applications, the PC market is poised to subsist primarily on lukewarm replacements in the future.

“The second quarter of 2013 was the third consecutive quarter where the U.S. market came through stronger than the worldwide market. This was largely due to some recovery in the overall economy and channel inventory replenishment,” said Rajani Singh, research analyst, Client Computing. “Following the stronger than expected 2Q13, we expect the second half of 2013 to restore some volume momentum driven largely by better channel involvement of top vendors and industry restructuring/alignment. We also anticipate operating system migration (Window XP to 7) will drive some volume in the commercial segment. Entry-level ultraslim systems and lower-priced convertibles will also be bright spots in an otherwise still troubled consumer market.”

Three fundamental shifts


July 10, 2013

By Pete Singer, Editorial Director

At The ConFab last week, Dr. Gary Patton, vice president, semiconductor research and development center at IBM, said there is a bright future in microelectronics (I heartily agree). He said that although there seems to be a fair amount of doom and gloom that scaling is ending and Moore’s Law is over, he is very positive. “There are three huge fundamental shifts that are going to drive our industry forward, will drive revenue growth and will force us to keep innovating to enable new opportunities,” he said.

The first fundamental shift is the explosion of applications in the consumer and mobile space. Patton noted examples such as cars that can drive themselves and can detect people and bicyclists and avoid them, smart phones for as little as $25, wearable devices that not only tell you what you’re doing but how you’re doing, and 4K television. “That is an incredible TV system, but it’s going to demand a lot of bandwidth; twice the bandwidth that’s out there today. If you turn on your 4K system, your neighbors are going to start to notice it when they try to access the internet,” he said.

Patton said that it’s estimated that today there are about 12.5 billion devices connected to the internet. That’s expected to grow to $30 billion by 2020. This represents the second fundamental shift commonly known as Big Data. “All these interconnected devices are shoving tremendous amount of data up into the cloud at the rate of 1.5 Exabytes (1018) bytes of data per month,” Patton said. “And that’s grown by about an order of magnitude in just the last 13 years. The estimate is that in the next 4 years, it’s going to go up another order of magnitude. It’s accelerating.”

The third fundamental shift is with all this data going up into the cloud, the data is almost all unstructured data, such as video and audio. “It’s related data but disconnected. How do we take that data and do something with it? That brings us to analytics and cognitive computing. We have really just started in this arena.”

So there you have it. Three reasons to be very positive about the future of the semiconductor industry: an explosion of applications, the rise of big data and the need to analyze all that data.

450mm Status Report


April 3, 2013

The switch to 450mm will be the largest, most expensive retooling the semiconductor industry has ever experienced. Will you be ready? 450mm fabs, which will give an unbeatable competitive advantage to the largest semiconductor manufacturers, are likely to cost $10 billion and come on-line in 2017, with production ramp in 2018. Unprecedented technical challenges still need to be overcome, but work is well underway at an R&D center in upstate New York, at the Global 450mm Consortium, G450C, and at the imec consortium in Europe. Hear from the G450C General Manager, Paul Farrar Jr., on the current status of activities, key milestones and schedules, and imec’s senior business development director, Lode Lauwers, on why 450mm is important for Europe, and the status of 450mm research on processes and devices.

This event was originally broadcast on March 5th, 2013 and is now available for on-demand viewing.

As the semiconductor industry moves toward smaller geometries, manufacturing processes are becoming more complex. In particular, they’re more demanding of all the variable parameters on a process tool, including process gas accuracy. Cutting down on variability in the process positively impacts productivity and yield.

Mass flow controllers (MFCs) are critical to maintaining process control.  Now, next generation MFCs like the GF135 from Brooks Instrument are enabling a leap forward in advanced process gas chemistry control. This technology optimizes semiconductor manufacturing processes while moving quality control upstream with features like:

• Integrated rate-of-decay (ROD) flow-error detection without process disruption, identifying and correcting issues before they happen, preventing wasted time and wasted wafers
• Improved process gas accuracy
• Enhanced pressure transient insensitivity (PTI) for critical processes
• Zero stability trending and correction ensuring accuracy at critical low flow set points
• Ultra-fast flow settling time for reduced process cycle time

Learn how you can improve your process yield and uptime – and your bottom line.