Category Archives: Uncategorized

Front-end fab equipment spending (including new, used, and in-house) is projected to increase 3.7 percent in 2016 (to US$ 37.2 billion) and another 13 percent in 2017 (to $42.1 billion) according to most recent edition of the SEMI World Fab Forecast.  Fab equipment spending for 2015 ended almost flat ($35.9 billion), with a slight decrease of -0.4 percent year-over-year.

The SEMI World Fab Forecast report presents details of fab-related spending through the industry and extends the outlook through the end of 2017.  Fab equipment spending is expected to pick up slowly in the first half of 2016, and accelerate into the second half when momentum starts to build for 2017, with a return to double-digit growth rates (see Figure 1).

Figure 1

Figure 1

The biggest contributors to the growth are foundries, 3D NAND fabs, and companies beginning to equip and prepare for the 10nm ramp-up in 2017. Dedicated foundries continue to represent the largest spending segment. Spending for 2015 dropped slightly from $10.7 billion to $9.8 billion (-8 percent YoY), but is expected to increase by 5 percent in 2016 and almost 10 percent in 2017.

DRAM spending ranks second place after foundries. After a strong 2015, DRAM spending is expected to slow in 2016 (-23 percent) and increase again in 2017 by 10 percent.

In terms of spending growth rates, the big momentum comes from 3D NAND (including 3D XPoint). Spending doubled from about $1.8 billion in 2014 to $3.6 billion in 2015, 101 percent growth. In 2016, it will again rise to more than $5.6 billion (50 percent growth).

The increase in equipment spending is also supported by six companies, which are among the top 10 spenders globally. The six have announced plans to increase their respective capital expenditures in 2016, while the assumption for the largest spender, Samsung, is that capital expenditure will be less than in 2015.

Equipment spending growth for 2017 is also buoyed by new 24 facilities (excluding R&D) which began construction in 2015 or will begin construction this year. These projects are located around the world, including eight planned in China alone.

The industry has recently set records for mergers and acquisitions, and more are expected in 2016.  The combined flat growth for semiconductor equipment spending in 2015 and slow growth in 2016 confirm a more mature industry.  New technologies — new nodes and newer memory devices — will drive the increase in spending currently forecasted for 2017.

Learn more about SEMI fab databases at: www.semi.org/en/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

Qioptiq, an Excelitas Technologies company introduces the LINOS Low-outgassing Faraday Isolators, the first of their kind. Developed for use in enclosed and high-power laser systems across the UV to green and NIR wavelengths, these Low-outgassing Isolator modules extend the service life and enhance the reliability of optical systems into which they are integrated.

faraday isolator

Faraday Isolators are used to protect lasers from damaging back-reflected light and to decouple seed lasers from amplifier stages. Furthermore, they are used to increase power stability, reduce optical noise and prevent laser damage. LINOS FI-405-3SC LO and FI-1030-3SC LO Low-outgassing Faraday Isolators use optically-contacted polarizers to create a high damage threshold while delivering excellent isolation of 33dB and a high transmittance. They are especially suitable for enclosed laser systems, vacuum systems, and high-power lasers in semiconductor processing environments.

These Low-outgassing Faraday Isolators typically emit 25 times less volatile organic compounds (VOCs) than conventionally produced Faraday Isolators. They feature a 3.5mm clear aperture and a patented magnet system which enables an exceptionally compact design footprint. They are available for 405nm and 1030nm, with custom wavelength designs available upon request.

“In the past, low-outgassing properties were almost exclusively needed for space and scientific, ultra-high vacuum applications,” said Ian Alcock, Vice President of Excelitas Optics & Laser Technology business unit. “Today, with the continual demand for ever higher laser powers, the challenge of minimizing contamination or damage of laser optics is becoming increasingly relevant for more and more applications. Our latest low-outgassing products have been specifically designed to address this challenge.”

New Low-outgassing Faraday Isolators are the latest additions to the field proven line of LINOS Faraday Isolators from Qioptiq, an Excelitas Technologies Company. For many years, LINOS Faraday Isolators have been meeting customers’ needs in numerous applications across industrial manufacturing, research & development and life sciences. Due to their superior optical performance and high mechanical stability, LINOS Faraday Isolators are chosen by professionals all over the world.

BY ED KORCZYNSKI, Sr. Technical Editor

Industrial Technology Research Institute (ITRI) worked with TSMC in Taiwan on a clever in-line monitor technology that transforms liquids and automatically-diluted-slurries into aerosols for subsequent airborne measurements. They call this “SuperSizer” technology, and claim that tests have shown resolution over the astounding range of 5nm to 1 micron, and with ability to accurately represent size distri- butions over that range. Any dissolved gas bubbles in the liquid are lost in the aerosol process, which allows the tool to unambiguously count solid impurities. The Figure shows the compact components within the tool that produce the aerosol.

Semiconductor fabrication (fab) lines require in-line measurement and control of particles in critical liquids and slurries. With the exception of those carefully added to chemical-mechanical planarization (CMP) slurries, most particles in fabs are accidental yield-killers that must be kept to an absolute minimum to ensure proper yield in IC fabs, and ever decreasing IC device feature sizes result in ever smaller particles that can kill a chip. Standard in-line tools to monitor particles rely on laser scattering through the liquid, and such technology allows for resolution of particle sizes as small as 40nm. Since we cannot control what we cannot measure, the IC fab industry needs this new ability to measure particles as small as 5nm for next- generation manufacturing.

There are two actual measurement technologies used downstream of the SuperSizer aerosol module: a differ- ential mobility analyzer (DMA), and a condensation particle counter (CPC). The aerosol first moves through the DMA column, where particle sizes are measured based on the force balance between air flow speed in the axial direction and an electric field in the radial direction. The subsequent CPC then provides particle concentration data.

Combining both data streams properly allows for automated output of information on particle sizes down to 5nm, size distributions, and impurity concentra- tions in liquids. Since the tool is intended for monitoring semiconductor high-volume manufacturing (HVM), the measurement data is automatically categorized, analyzed, and reported according to the needs of the fab’s automated yield management system. Users can edit the measurement sequences or recipes to monitor different chemicals or slurries under different conditions and schedules.

When used to control a CMP process, the SuperSizer can be configured to measure not just impurities but also the essential slurry particles themselves. During dilution and homogeneous mixing of the slurry prior to aerosol- ization, mechanical agitation needs to be avoided so as to prevent particle agglomeration which causes scratch defects. This new tool uses pressured gas as the driving force for solution transporting and mixing, so that any measured agglomeration in the slurry can be assigned to a source somewhere else in the fab.

Screen Shot 2016-02-22 at 9.58.58 AM

TSMC has been using this tool since 2014 to measure particles in solutions including slurries, chemicals, and ultra-pure water. ITRI, which owns the technology and related patents, can now take orders to manufacture the product, but the research organization plans to license the technology to a company in Taiwan for volume manufacturing. EETimes reports that the current list price for a tool capable of monitoring ultra-pure water is ~US$450k, while a fully-configured tool for CMP monitoring would cost over US$700k.

IWLPC Insights


February 1, 2016

BY PHIL GARROU, Contributing Editor

The 12th annual International Wafer Level Packaging Conference (IWLPC) was held in San Jose in October. The technical focus consisted of 1) fan-out WLCSP, 2) 2.5 and 3D IC packaging, and 3) MEMS. This conference is becoming a major player in the exhibition end of the packaging business this year having 65 booths set up in San Jose. Here’s a review of the news in these areas.

DECA

Cost, yield and reliability issues have effectively limited the widespread adoption of FOWLP. Placing singulated chips on the carrier to form the molded panel requires high placement accuracy. Any misplacements can lead to pattern overlay diffi- culties in the buildup process on the reconstituted panel. The requirement for high placement accuracy restricts throughput at the pick-and-place operation, leading to high process costs. During the molding operation and mold cure, die drift or movement can occur. This die drift can further complicate pattern overlay matching in the buildup process on the panel and can result in yield loss when the drift is excessive.

In the DECA process die with preformed Cu studs are placed face-up on a carrier, using a high speed pick and place tool. The front and sides of the die are then covered with mold compound using compression molding. The molded panel is debonded from the carrier, and the front surface is ground to reveal the Cu studs. A high speed optical scanner is used to determine the actual position of every die on the panel. This information is fed into a proprietary Adaptive Patterning design tool, which adjusts the fan-out unit design for each package on the panel to match actual die locations. Finally, the design files for each panel are imported to a lithography machine which uses the design data to dynamically apply a custom, Adaptive Pattern to each panel during the fan-out build-up process. Adaptive Patterning works by dynamically adjusting one or more build-up layers to accurately connect to the Cu studs protruding through the mold compound for each individual die in the molded panel.

SPTS – Plasma dicing

Plasma dicing is attracting significant interest within the semiconductor industry as a viable alternative to conven- tional singulation methods using saw blades or lasers. Plasma dicing promises benefits such as increasing wafer throughput, die per wafer and die yields (due to low damage processing). For small die, in particular, where the time required for a high number of mechanical slices in “series” can be substantial, a “parallel” process such as plasma dicing which etches all dicing lanes simultaneously, can significantly increase wafer throughput.

Maximum benefits are gained when plasma dicing is “designed in” from the beginning. With dicing lanes defined by photolithography, these lanes can be narrower than the width of a dicing blade, saving valuable silicon real-estate which can be used to increase the number of die per wafer. Also, the designer can make sure that dicing lanes are free from metals and other layers which can hinder plasma etching. This is often quoted as the prime challenge which prevents implementing plasma dicing in an existing production scheme.

IMEC/KLA-Tencor

IMEC/KLA-Tencor shared their results on investigations to determine the best way to insure μbump presence and co-planarity. μbump dimensions are being scaled down to 20 μm pitch (10 μm in width and 8 μm high). For die-to-die and die-to-wafer stacking, the need for highly accurate and repeatable measurement of μbumps at both die-level and wafer- level is a must for this technology to become a viable industrial option. Bump co-planarity is defined as the difference between the heights of the tallest and the shortest μbump within a die.

A failure to properly characterize the co-planarity of each die and detect defects of interest such as damaged, missing or mis-located bumps can lead to the wrongful classification of the die as suitable for assembly. This may have a number of yield-affecting consequences during stacking, such as open and short circuits, die cracking and thermal sinks. As the number of die in a typical die stack increases, a single falsely classified die will affect the entire product.

One of the challenges in constituting a meaningful subset for measurement is to define a population of μbumps which is large enough to be statistically significant and to select μbumps from areas in the die which will represent height range and copla- narity of the full die.

By PETE SINGER, Editor-in-Chief

Consolidation in the semiconductor industry continues apace, with more than $100 billion in mergers and acquisitions announced in 2015, and more to come in 2016 (versus $62.6 billion of 2010 to 2014 combined).

“With our industry growth rates being so low, it’s a lot cheaper to acquire market share than it is to invest and beat your competitor over the head,” said analyst Bill McClean, speaking at SEMI’s Industry Strategy Symposium (ISS) in January.

One potentially negative impact of consolidation is reduced innovation, said Ivo J. Raaijmakers, Chief Technology Officer and Director of R&D at ASM International, speaking at ISS on consolidation in the equipment supplier market. “The tail has been cut off. A lot of innovation happens in this tail,” he said. “The question we have to ask ourselves is how can we ensure efficient innovation in such a consolidating landscape of equipment suppliers?”

The challenge is compounded by exponentially increasing chip complexity and R&D spending, along with rapid increases in material diversity.

Raaijmakers provided an equation that captures the mathematics of

innovation:

dI/dt α I x η/τ

where I is the number of innovations being worked on: loosely relates to R&D budget

η is the average success rate: what fraction of projects are successful, and τ is the time constant: how long does it take from innovation to production

He noted that Industry consolidation lowers the number of innovation projects, the success rate decreases with complexity, and development time increases with complexity. “We are in deep trouble, unless we manage η and τ,” Raaijmakers said.

There’s not much hope in reducing the time constant. New developments have historically taken 7-10 years on average from conception to high volume production. “Can we decrease this by collaboration along the value chain? I think it will be difficult and if you can do it, it will not be a huge gain,” Raaijmakers said.

On the other hand, there’s much to be gained by increasing the efficiency factor, and collaboration can be effective here. “Collabo- ration along the innovation chain can significantly lower the risk of adoption, increase the success rate, and may increase the speed,” Raaij- makers said. “Are we all working on the right things to push through into manufacturing? How quickly can you narrow down choices?”

Raaijmakers said a company needs to be ambidextrous. “You have to be good at taking things into volume production and supporting it there. And you have to be good in R&D. Maintaining those two traits is not so easy,” he concluded.

AirProducts-logo-pms347-JPG

Epicor-logo-Business Inspired-2color-CMYK

Date: January 19, 2016 at 1 p.m. ET

Free to attend

Length: Approximately one hour

NEW register_button

The age of the Internet of Things is upon us, with the expectation that tens of billions of devices will be connected to the internet by 2020. This explosion of devices will make our lives simpler, yet create an array of new challenges and opportunities in the semiconductor industry, and in manufacturing industries in general. At the sensor level, very small, inexpensive, low power devices will be gathering data and communicating with one another and the “cloud.” On the other hand, this will mean huge amounts of small, often unstructured data (such as video) will be rippling through the network and the infrastructure. The need to convert that data into “information” will require a massive investment in data centers and leading edge semiconductor technology.

Also, manufacturers seek increased visibility and better insights into the performance of their equipment and assets to minimize failures and reduce downtime. They wish to both cut their costs as well as grow their profits for the organization while ensuring safety for employees, the general public and the environment.

The Industrial Internet is transforming the way people and machines interact by using data and analytics in new ways to drive efficiency gains, accelerate productivity and achieve overall operational excellence. The advent of networked machines with embedded sensors and advanced analytics tools has greatly influenced the industrial ecosystem.

Today, the Industrial Internet allows you to combine data from the equipment sensors, operational data , and analytics to deliver valuable new insights that were never before possible. The results of these powerful analytic insights can be revolutionary for your business by transforming your technological infrastructure, helping reduce unplanned downtime, improve performance and maximize profitability and efficiency.

RajeevRajeev Rajan, Vice President of Product for Internet of Things (IoT) at GLOBALFOUNDRIES

Rajeev Rajan is the Vice President of Product for Internet of Things (IoT) at GLOBALFOUNDRIES. He is responsible for driving thought leadership and awareness of GLOBALFOUNDRIES’ IoT solutions, which revolves around supporting go-to-market plans across the IoT portfolio as well as providing strategic direction and new market opportunities.

Prior to joining GLOBALFOUNDRIES, Rajeev was Sr. Director, Product Management and Marketing at Qualcomm Life Inc, where he led the product management and strategy for the company’s IoT/IoE and Healthcare and Life Sciences. Rajeev has also held positions of Co-Founder and CTO of 2net™, a Digital Health/mHealth/Wireless Healthcare start-up company, which has become the multi-million dollar Qualcomm healthcare company. He has held multiple technology, product, and business strategy roles at Qualcomm.

He holds more than 35 patents and is a co-author of the book Wireless Health: Remaking of Medicine by Pervasive Technologies. He currently serves as an Industrial Advisory Board Member of the Advanced Platform Technology (APT) Center, United States Department of Veterans Affairs (VA).

Rajeev holds a BS in Physics from St. Xavier’s College and a MS in Computer Science from Sardar Patel University, in Gujarat, India. He received his Executive MBA from the Rady School of Management at the University of California San Diego, CA and a MS in Biomedical Engineering from Case Western Reserve University in Cleveland, Ohio.

UdayTennetyUday Tennety, Director, Strategic Engagements and Innovation, GE Digital

Uday Tennety manages the strategic client engagements at GE Digital, and also leads a customer innovation and co-creation center called the Design Center. Uday has over 15 years of experience in providing enterprise software solutions to clients in various industries including Telecom, Energy, Transportation, Retail, Insurance, Finance, Banking and Software.

Prior to joining GE, Uday worked as the Director of Analytic Services at Revolution Analytics, a Microsoft company, where he helped many Fortune 500 companies with their Big Data Analytics initiatives. In the past, Uday also worked at companies such as Fujitsu, Tata Consultancy Services, Ecologic Analytics and others where he led diverse teams with roles in Strategy, Business Development, Marketing, Product Management and Product Development. Uday holds a MS in Computer Science degree from the University of North Carolina at Charlotte, and an MBA from the Haas School of Business at UC Berkeley.

Sponsored by Air Products and Epicor Software Corporation

Air Products has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  www.airproducts.com/advancing

Epicor Software Corporation is a global leader delivering inspired business software solutions to the manufacturing, distribution, retail and services industries. With over 40 years of experience serving small, midmarket and larger enterprises, Epicor enterprise resource planning (ERP), production control software (MES), and supply chain management (SCM), enable companies to drive increased efficiency and improve profitability. With a history of innovation, industry expertise and passion for excellence, Epicor provides the single point of accountability that local, regional and global businesses demand. www.epicor.com/electronics

AirProducts-logo-pms347-JPG

Date: December 16, 2015 at 12:00 p.m. ET

Free to attend

Length: Approximately one hour

NEW register_button

NAND Flash has become the non-volatile memory of choice for smart phones, tablets and solid state drives. The success of NAND in these markets has been driven by a relentless improvement in cost per bit by continually shrinking lithographic features for 2D planar NAND. This lithography driven model for 2D NAND is now breaking down and 3D has entered the market as the NAND solution of the future. In the first segment of the Webinar we will discuss how NAND flash has gotten to where it is today and the current technical limitations. This will set the stage for the second segment addressing 3D NAND.

Flash memory has revolutionized the world of solid-state data storage, mainly because of the advent of NAND technology. Started in multimedia applications for the consumer market (cell phones, audio players, digicam, USB sticks…) the technology has recently migrated also in the laptop and tablets market as well as in enterprise storage and server farms where it has become an indispensable component in the memory hierarchy of large storage systems. Especially the latter is a major growth market, which will propel Flash into the Terabit era.

However, from the technical point of view, this requires a major change in how these memories are being fabricated. The floating gate concept which has been the old ‘work horse’ for the entire nonvolatile memory market since the 60s until today, has finally run out of steam because of major physical limitations with respect to the device electrostatics. Therefore, the industry has been looking for alternatives for many years (Phase Change memory, Spin-based Magnetic memory, Ferroelectric memory, Resistance RAM, micromechanical memory, nanocrystal memory, TANOS, etc). Finally, the winner concept turns out to be the 3D or vertical NAND concept which is based on the stacking of vertical gate-all-around (GAA) devices with a nitride charge trapping layer. While the other ‘emerging’ memory types mentioned above are narrowed down to other application areas such as embedded memories and storage class memories (SCM), the 3D NAND has created a new roadmap which is no longer solely linked to the lithography roadmap but rather to a combination of parameters such as cell diameter, vertical cell pitch, numbers of cells in a stack and the number of bits per cell.

This presentation will discuss this (r)evolution as well as its major scaling limitations.

Speakers:

jan van houdtProf. Dr. Jan Van Houdt, IEEE Fellow

Jan Van Houdt received a MSc degree in Electrical and Mechanical Engineering and a PhD from the University of Leuven. During his PhD work, he invented the HIMOS™ Flash memory, which he transferred to several industrial production lines. In 1999 he became responsible for Flash memory at imec and as such was the driving force behind the expansion of imec’s Memory Program. Today he is Chief Scientist in the Process Technology unit of imec. He has published more than 250 papers in international journals and accumulated more than 200 conference contributions (incl. 35 invitations and 5 best paper awards). He has filed more than 50 patents and served on the program and organizing committees of 10 major semiconductor conferences. In 2014 he received the title of IEEE Fellow for his contributions to Flash memory devices. Recently, he was appointed a part-time professor in Electrical Engineering and Nanotechnology at the University of Leuven.

ScottJ crop 72dpiScott Jones, Founder and President, IC Knowledge

Scotten (Scott) W. Jones has nearly 30 years of experience in the semiconductor and MEMS industries, 18 of those in senior management positions. He holds a BS in Physics from the University of Rhode Island, has published dozens of papers, books and book length reports and holds two patents. His career focus has been on manufacturing and process technology. Scott’s responsibilities have included manufacturing, engineering, IT, technology development, finance and accounting. Scott has built or upgraded several wafers fabs and has extensive experience in manufacturing execution systems, cost modeling, IP licensing agreements, outsourcing and foundry relationships. Scott’s management positions have included Vice President and Co-General Manager of a Semiconductor Division, Vice President of Operations at a Semiconductor Company and Vice Presidents of Engineering and Vice President of Operations at a MEMS Company. Scott is a senior member of the IEEE and is a lifetime member of Strathmore’s Who’s Who. In addition to serving as President of IC Knowledge, he also serves as a Director of the Georgetown Education Foundation.

Sponsored by Air Products

Air Products has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  www.airproducts.com/advancing

BY PETE SINGER, Editor-in-Chief

The semiconductor industry is sure to benefit by the “digitization” of manufacturing in that it’s an important component of the IoT explosion, along with smart homes, smart cities, smart health, etc. But is the semiconductor manufacturing industry – already one of the most advanced in the world – ready for the Industry 4.0 revolution? Will the cobbler’s children get new shoes?

I believe it will, but there are some major roadblocks that need to be overcome.

New innovation is required for a couple of reasons. First, the path to continued cost reduction through scaling has come to an end. The industry will continue to push to smaller dimensions and pack more functionality on a single chip because the world will always need super- advanced electronics for data servers, cloud computing and networking. But it’s looking to be an increasingly expensive proposition.

At the same time, the industry is looking to the Internet of Things explosion as the “next big thing.” The two most important aspects of IoT devices will be low power and low cost. Speaking at a press conference at Semicon Europa in October, Rutger Wijburg, Senior VP and General Manager Fab Manufacturing for GlobalFoundries said a typical figure of merit in the mobile space is $0.25/mm2. “My estimation is that the massive volume going into the Internet of Things has to be delivered for ASPs (average selling price) between $0.05 and $0.10/mm2,” he said.

Could the Industry 4.0 movement enable a dramatic reduction in costs? Proponents say greater connectivity and information sharing — enabled by new capabilities in data analytics, remote monitoring and mobility — will lead to increased efficiency and reduced costs. There will also be greater efficiency across the supply chain.

Sadly, there’s a long way to go for the semiconductor industry to realize the kind of data sharing and “digitization” embodied in the Industry 4.0 concept. The main challenge is that the semiconductor industry has been so secretive, especially when it comes to process recipes and yield data, that 4.0-type of data sharing is almost impossible. What’s needed? A whole new strategy for looking at IP and deciding what is critical and what can be shared.

19. Atom-by-Atom Modeling of Grain Boundaries
Category: Noteworthy Papers on Diverse Topics
Paper 5.6 – Statistical Poly-Si grain boundary model with discrete charging defects and its 2D and 3D implementation for vertical 3D NAND channels; Robin Degraeve et al, Imec

Click image for full-size view.

Click image for full-size view.

Future flash memories may be stackable devices with polysilicon channels running vertically through them. However, defects in polysilicon’s crystal structure called grain boundaries decrease electrical conductivity by scattering and trapping electrons. A good understanding of the actual conduction paths in these channels would enable more accurate predictions of how the devices will operate. Existing computer models of these paths, though, are based on generalized assumptions about grain boundaries. An Imec team will present a new atomistic 3D model of grain boundaries that takes into account specific regions of enhanced scattering in the polysilicon, plus specific charge defects that can cause local barriers and depletion areas. The model gives statistical insight into the properties of scaled poly-Si channel devices (particularly vertical NAND devices), and their yield and reliability limitations.


HOME [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]

11. RF CMOS Circuits on Flexible, Application-Specific Substrates
Category: Physically Flexible Electronics
Paper 15.7 – Application-Oriented Performance of RF CMOS Technologies on Flexible Substrates; Justine Philippe et al, IEMN/STMicroelectronics/CEA LETI Minatec

Click image for full-size view.

Click image for full-size view.

Although physically flexible circuitry would enable innovative wearable, biomedical, security and other products, flexible circuits so far have demonstrated only limited performance. That’s because high-performance CMOS devices are fabricated using harsh high-temperature processes that damage most flexible materials. A team led by France’s Institut d’Electronique de Microélectronique et de Nanotechnologie, though, has developed what they call an ultimate thinning and transfer-bonding (UTTB) process which they used to build radio-frequency CMOS circuits on a variety of flexible substrates: polyimide plastic film, glass, and stainless steel. First they built RF CMOS circuits on an SOI substrate, then they thinned it to 30µm by completely removing the backside. The circuits were then transferred to the various substrates using a laminating process. For plastic and glass substrates, the circuitry was attached by laminating it using a dry polymer film and rollers. For stainless steel substrates, a 400nm–thick indium layer was first deposited, and then the circuits were laminated to it in a similar manner. The small-signal performance of these devices wasn’t significantly degraded from what it had been on the original substrate, and unwanted harmonics were actually reduced. The researchers say their UTTB technique can be adapted to meet application-specific requirements for ultra-mechanical flexibility, heat dissipation and transparency.


HOME [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] NEXT