12. Flexible Circuits Built from 2D Nanomaterials
Category: Physically Flexible Electronics
Paper 32.1 – High-Frequency Prospects of 2D Nanomaterials for Flexible Nanoelectronics from Baseband to Sub-THz Devices; Saungeun Park et al, University of Texas at Austin

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Crystalline materials consisting of a single layer of atoms are referred to as two-dimensional (2D) materials. A University of Texas team will present an in-depth look at the prospects for flexible electronics based on 2D materials such as graphene, phosphorene and transition metal dichalcogenides (TMDs). The authors will describe how in a wide range of experiments they achieved high performance from these nanomaterials on flexible substrates. Target applications, which could include wearable devices and Internet-of-Things components, cover a large frequency spectrum encompassing low-power RF, microprocessors, transceivers and THz electronics. The authors suggest that the large number of available 2D materials with vastly different physical properties will allow custom designing of circuit functions tailored to specific applications. They envision flexible nanosystems built from the heterogeneous integration of semiconducting, semimetallic and insulating 2D materials.

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13. Multiband Imaging in One Device
Category: Displays and Imaging
Paper 30.1 – Multi-Storied Photodiode CMOS Image Sensor for Multiband Imaging with 3D Technology; Y. Takemoto et al, Olympus

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There is a growing demand for integrated imaging systems that can simultaneously capture both red-green-blue (RGB) visible light and near-infrared (NIR) wavelengths that contain range-finding, or depth-of-field, information. In medicine, for example, the ability to capture all of these wavelengths simultaneously with one compact device would make it easier and less time-consuming to identify and pinpoint a wide range of targets in different parts of the body, such as pathological lesions. Until now, however, trying to detect both RGB and NIR signals on the same chip would compromise either one or the other. Researchers at Olympus will detail how they used 3D wafer-stacking technology to integrate two separate CMOS imagers into one device, each optimized for either RGB or NIR through a careful balance of active silicon thickness and pixel size. The top imager is optimized for visible detection with an array of small pixels and a thinned 3µm active silicon layer. NIR signals pass through it to reach the bottom imager, which is optimized for NIR detection with an array of larger pixels and thick active silicon. The researchers say there is no degradation in color reproduction, sensitivity or resolution.

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14. Artificial Synapses for Learning
Category: Brain-like Computing
Paper 17.1 – NVM Neuromorphic Core with 64k-cell (256-by-256) Phase Change Memory Synaptic Array with On-Chip Neuron Circuits for Continuous In-Situ Learning; S. Kim et al, IBM

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Advances in machine learning and neuroscience have sparked growing interest in neuromorphic (brain-inspired) computing, and a number of neuromorphic circuits have been demonstrated that are capable of functions such as pattern-recognition. At the IEDM, IBM researchers will describe a chip that may bring neuromorphic computing closer to true artificial intelligence: the largest neuromorphic “core” ever built, a 256 x 256 array of artificial synapses with on-chip programming circuitry. It may be capable of “deep learning,” which is when machines follow sophisticated algorithms in an attempt to mimic brain functions like seeing, listening and thinking. The synapses are 64k-cell phase-change memory (PCM) devices, and the researchers say that each PCM synapse is capable of running in one of three modes independently, each of which is an analog of the behavior of real neurons: 1) so-called leaky-integration-and-fire (the synapse fires when input voltage reaches a certain threshold); 2) spike-timing dependent plasticity (an algorithm that mimics a fundamental brain mechanism for learning and memory; and 3) in idle mode. The researchers say that once wiring issues are solved the array size potentially could be increased to the biological scale.

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15. Vacuum Nanoelectronics Integrated with Silicon
Category: Noteworthy Papers on Diverse Topics
Paper 33.1 – High Performance and Reliable Silicon Field Emission Arrays Enabled by Silicon Nanowire Current Limiters; Stephen Guerrera et al, MIT

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Vacuum electronics technology may sound like ancient history but a team from MIT has used a modern variant to make some very futuristic devices. They are nanoscale cold cathodes (tiny electron guns) built from arrays of nanowire field emitters that can be integrated with traditional silicon technology. The integrated devices may enable compact new RF amplifiers and sources of terahertz, infrared and X-ray energy. They combine the positive aspects of solid state semiconductors (high gain and low noise) with those of vacuum electronics (high power and efficiency). They demonstrated a current density of >100 A/cm², more than a hundredfold greater than any other field-emission cathode operated in continuous wave mode. At the same time, the devices also exhibited long lifetimes and low-voltage operation. Each emitter (6-8nm tip diameter) sits atop a vertical silicon nanowire (10µm tall, 100-200nm in diameter). The nanowire acts as a current limiter to protect the emitter from possible damage from heating and arcing. The team built emitter arrays as large as 1,000 x 1,000.

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16. Moore’s Law in Neural Science?
Category: Noteworthy Papers on Diverse Topics
Paper 29.5 – High Density Optrode-Electrode Neural Probe Using SixNy Photonics for In Vivo Optogenetics; Luis Hoffman et al, Imec/KU Leuven

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Optogenetics is a technology used to study neurons by interacting with them using visible light to stimulate their constituent proteins. The neural cells aren’t damaged, as they can be when electrically stimulated. A team led by Imec will discuss an implantable neural probe that has the highest reported density of optrodes (light emitters) and electrodes (to record the responses of the neurons once they are stimulated). As with CMOS digital devices, neural probes benefit from high integration densities, which are enabled by decreasing feature sizes. Higher density leads to better spatial resolution and also enables smaller probes that are less likely to damage tissue. To build the probe, the researchers integrated two different CMOS processes (silicon nitride photonics and TiN electrodes). They built probes 100µm wide and 30µm thick, containing 12 optrodes (6 x 20 µm² in size) and 24 electrodes (10 x 10 µm²). They packaged the circuitry, implanted it in a mouse brain and successfully demonstrated that it could both drive and record neural activity.

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17. 3D Views of Nanoscale Devices
Category: Noteworthy Papers on Diverse Topics

Two noteworthy IEDM papers will describe different ways to generate highly accurate 3D views of extremely small devices, as an aid to ultimately boosting their performance.

3D Maps of TFET Heterojunctions
Paper 14.2 – Tunnel Junction Abruptness, Source Random Dopant Fluctuation and PBTI Induced Variability Analysis of GaAs0.4Sb0.6/In0.65Ga0.35As Heterojunction Tunnel FETs; R. Pandey et al, Pennsylvania State University

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Tunneling field-effect transistors (TFETs) are an emerging technology based on principles of quantum mechanics. TFETs are promising for ultra-low-power applications but improvements in their performance and reliability are needed. Critical to TFET performance when they are made from combinations of III-V materials is the need for abrupt and uniform interfaces among the dissimilar materials. Variability at these interfaces, or heterojunctions, reduces device performance. It is difficult to characterize heterojunctions with precision in nanometer-scale devices, but a Penn State team used atom probe tomography and time-of-flight spectroscopy to do so. First they cooled TFET samples to 50° Kelvin. Then, they rapidly heated the heterojunction under study with laser pulses to evaporate layers of atoms from it, one layer at a time. They captured the atoms from each layer in an electric field, and then performed spectroscopic analysis to identify the individual atoms which constituted each layer. From all this data they built a 3D map of the heterojunction, with a resolution of 2.4nm. They also studied two other sources of variability in TFETs—random dopant fluctuations and the interface between the channel and the ultra-thin high-k gate dielectric—with an eye toward further improvements.

3D Carrier Profiling in 10nm FinFETs
Paper 14.1 – Scalpel Soft Retrace Scanning Spreading Resistance Microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET; Pierre Eyben et al, Imec

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In solid state devices, electrons and holes are generically called charge carriers. As 3D devices such as FinFETs scale to the 7nm and 5nm nodes, fewer charge carriers are available. Because their distribution is not uniform, it becomes critical to establish correlations between their actual locations within the 3D architecture and the device’s electrical performance. Once these correlations are known, the architecture can be modified for better performance. Scanning Spreading Resistance Microscopy (SSRM) is a technique that uses a probe to measure a surface’s electrical resistance and thus the density of charge carriers at any given point on the surface. An Imec team will discuss a variation of the technique they call Scalpel SSRM, which uses diamond-based probe tips to scrape off material as the surface is repeatedly scanned on all sides, thus probing deeper into the material layer by layer. They used the resulting data to produce accurate 3D maps of the density of charge carriers throughout sub-10nm FinFETs. They say their existing technique can be used to profile carrier density in 3D devices as small as 4nm, and that it has the potential to achieve a resolution of just 1nm, which would make it useful for characterizing extremely small future architectures such as gate-all-around arrangements and nanowires.

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18. Better Modeling of STT-MRAMs
Category: Noteworthy Papers on Diverse Topics
Paper 28.5 – Physics-Based Compact Modeling Framework for State-of-the-Art and Emerging STT-MRAM Technology; Nuo Xu et al, Samsung

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Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising technology for future non-volatile, high-speed applications. But the internal magnetic dynamics of this new and complex technology aren’t completely understood, which poses a hurdle to optimizing and commercializing it. Computer modeling and simulation of STT-MRAMs is essential for a better understanding. However, until now building such complex models for circuit simulation has been laborious, time-consuming and prone to inaccuracy because it has relied on fitting to data from sample devices. Samsung researchers developed a simpler, more accurate computer modeling framework built from the essential physics. It enables the study of all possible magnetic interactions involved in the switching of the devices’ ferromagnetic layer, as well as charge transport and spin transfer torque interactions in magnetic tunneling junctions. The researchers verified the accuracy of their model by comparing it with actual data from 15nm STT-MRAMs. Their work will lead to better simulations of circuits and systems which incorporate these state-of-the-art devices.

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10. CMOS-Compatible Laser
Category: Silicon Photonics
Paper 2.6 – Direct Bandgap GeSn Microdisk Lasers at 2.5 µm for Monolithic Integration on Si-Platform; Stephan Wirths et al, Forschungszentrum Jülich/ Paul Scherrer Institute/ETH/University of Leeds/University of Grenoble/CEA LETI Minatec

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Silicon photonics is an evolving technology in which light, not wires, carries data within and among computer chips. Light can carry more data, faster, using less power than metal wires. Silicon is ubiquitous in electronics but it is a poor material for light-emitters like lasers, and the integration of lasers made from other materials into standard silicon CMOS devices is problematic. But if that could be done more easily, then much more powerful computers and other digital systems could be built. A research team from several European research organizations and universities, led by Germany’s Forschungszentrum Jülich institute, will report on a silicon-based direct-bandgap germanium-tin (GeSn) micro-disk laser that emits at a lasing wavelength of 2.5 μm at a power output of 221 kW/cm². The device was built using standard CMOS-compatible processing and was monolithically integrated on a silicon platform. Its 560-nm-thick GeSn epitaxial layers were grown on Ge buffers/Si substrates. Its lasing performance arises from 1) straining the epitaxial layers so they become direct bandgap materials; and 2) its micro-disk cavity architecture. The work is an important step toward integrated silicon photonics.

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9. Better GaN HEMTs for High-Power Amplifiers
Category: Power Devices
Paper 9.1, Collapse-Free High Power InAlGaN/GaN-HEMT with 3 W/mm at 96 GHz; K. Makiyama et al, Fujitsu/Tokyo Institute of Technology

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High electron-mobility transistors (HEMTs) made from GaN have great potential for use in high-power millimeter-wave amplifiers for high-data-rate wireless networks. Normally these transistors use an InAlN barrier layer to separate the channel from the source and drain. However, a team led by Fujitsu will show that InAlN is inadequate for devices intended for use in high-power amplifier applications because it facilitates “current collapse,” where a collection of electron traps occurs and alters the device’s performance. Instead, they used a higher-quality barrier material, InAlGaN. They also employed a novel double-layer SiN passivation technique. The 80nm-channel-length InAlGaN/GaN power HEMTs they built demonstrated a record 3 W/mm output power density at 96 GHz, which is a 60% improvement over the best results reported to date. Reliability also was superb. The power and reliability performance put the HEMTs at the state-of-the-art for use in W-band amplifiers (75–110 GHz).

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8. Monolithic 3D Chip
Category: 3D Devices and Circuits
Paper 25.4 – Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic, Memory and Sensor Analogy Circuitry for Internet of Things; Tsung-Ta Wu et al, National Nano Device Laboratories/National Tsing Hua University

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3D circuits often are made by stacking separate chips and connecting them electrically with through-silicon vias (TSVs), but TSVs have significant disadvantages including relatively narrow I/O bandwidth. Monolithic 3D ICs with no TSVs—where the devices in adjacent layers are directly connected—have been demonstrated, but transistor damage from thermal annealing can arise. That’s because each layer in a 3D device must be annealed to remove stresses in its crystalline silicon structure, and also to activate the dopants which have been implanted in it. However, the high heat involved with annealing (>1,000°C) can damage the devices that have already been built in lower layers. A team led by Taiwan’s National Nano Device Laboratories addressed this issue by using a CO₂ far-infrared laser at 400°C to selectively pulse-anneal specific areas of the silicon (the source-drain regions). They used this technique to build a sub-40nm monolithic IC containing a variety of heterogeneous functions—logic, SRAM, RRAM, sense and analog amplifiers, and gas sensors. No device degradation was reported, and the researchers say their technique is suitable for making the low-power, low-cost, small-footprint and heterogeneously integrated devices needed for the Internet of Things.

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