Issue



Build layers of protection for effective ESD management


10/01/2002







By Alan Learned, Ph.D.

When considering the appropriate level of electrostatic discharge (ESD) and electrical overstress (EOS) protection for a cleanroom, a cleanroom manager needs to develop an approach that uses systemic layers of protection tailored for the risk and threshold sensitivities in the operation. The strategy should also be based on an understanding of the ESD failure mechanisms involved as well as the protection technologies available.

Before building the layers of protection, put the problem into perspective: An ESD event can result in a range of unpleasant conclusions, from the destruction of integrated circuit devices to the contamination of pharmaceutical or biotechnology processes due to the electrostatic attraction and bonding of particles to charged surfaces.

Table 1 displays electrostatic voltage levels that can be generated by typical activities conducted in a cleanroom environment.1 Table 2 displays typical ESD withstand voltages, the maximum test voltage at which the device will not suffer damage, for a variety of semiconductor device technologies.2

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According to Table 1, electrostatic charges of 100 to 40,000 volts can be created by activities such as walking across a carpet, picking up a plastic bag from a bench top, or unwinding a roll of plastic packaging sheet. Table 1 also illustrates the effect humidity has on reducing the build-up of electrostatic charges.

Table 2 shows that magnetoresistive recording (MR) heads, for example, can be damaged by Human Body Model (HBM)-type electrostatic discharge levels as low as 10 volts. Withstand voltages for metal-oxide-semiconductor field effect transistors (MOSFETs), very large-scale integration (VLSI) and film resistor devices are in the 100- to 5,000-volt range.

How ESD damages electronics

The primary failure mode relates to the heat generated at points in the device as the electrical charge burst travels onto and through the component.

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Gate oxide failure occurs in the transistor when there is a breakdown of the dielectric between the gate and channel, resulting in excessive leakage or functional failure. A junction spiking failure will cause the migration of the metallization through the source/drain junction of metal oxide semiconductor (MOS) transistors, causing leakage or a functional failure. Latch-up failure can be initiated by ESD, creating an internal feedback effect that temporarily or permanently impacts circuit function.

There is no known practical way to screen for all forms of latent ESD damage in a device. To avoid this damage, devices must be given continuous ESD protection in a systemic, layered program that provides the appropriate protection for the level of risk, sensitivities and cost.

Building layers of protection

In cleanroom applications such as electronics that are becoming increasingly sensitive to ESD, one would need to build layers of protection into the overall operations plan.

Some of the elements of the plan will include front-end design for the devices; adequate grounding using a common ground point, wrist straps and footwear; static dissipative materials for garments, packaging, table mats, floor mats and flooring; air ionization to neutralize persistent charging at appropriate stages in the process; and training and auditing programs that ensure a good understanding of ESD risks and the procedures that reduce those risks.

Without specific protection circuitry designed into MOS devices, manufacturing of the systems would be extremely expensive, if not impossible. The typical approach is to protect inputs with current-limiting resistors and voltage-reducing elements that minimize the voltage and current of transients to a harmless level and dissipate the energy developed by them.

The designers, at the same time, must deliver this protection without decreasing the overall device performance in terms of speed or reliability. Printed circuit boards (PCBs), for example, are designed with decoupling capacitors, shielding and surge protection diodes to minimize the ESD hazard.

Grounding personnel and equipment is a baseline of defense for all ESD activities. Keeping all objects in a static protective area at the same electrostatic potential will provide the greatest protection of ESD-susceptible items.

Using a common point ground is a fundamental component of eliminating these potential differences. American National Standards Institute/Electrostatic Discharge Association (ANSI; Washington)/(ESDA; Rome, NY)-S20.20 recommends an AC impedence of <1.0 ohms for such a ground point. Wrist straps, flexible wrist bands with resistors in the ground cords, are used to ground personnel in the cleanroom and are recommended to perform in the range of 0.8¥106 to 1.2¥106 ohms.6

Conductive footwear, including heel/toe straps, boot straps, conductive boots and conductive shoes in conjunction with conductive or dissipative flooring, is necessary to eliminate static buildup. Footwear protection must be worn on both feet to be most effective and with a recommended resistance that is <1¥109 ohm.6

Cleanroom garments are designed to deliver static dissipation properties along with the particle barrier and low particle levels necessary for clean environments. For the garments to be an effective part of the ESD control system, the garments must be connected to a grounded surface, preferably to a common ground point if possible.

A surface resistivity range of 1¥105 to 1¥1011 ohms is recommended and if the garment is repeatedly laundered, verification of the static performance throughout its life cycle should be considered.6

Dissipative work surfaces, both table and floor mats, in the range of 1¥105 to 1¥109 ohms can ensure that charges can be removed at a safe rate, neither too fast nor too slow. ANSI/ESD-S20.20 recommends work surfaces deliver resistance levels of <1¥109 ohms.

The flexible and rigid packaging materials used in ESD-sensitive cleanrooms are chosen based on the threshold sensitivities of the contents, and can be designed to provide both static dissipation and shielding from electromagnetic interference (EMI) and radio frequency interference (RFI) effects. S20.20 recommends conductive packaging with <1¥104 ohms resistance and dissipative packaging performance in the >1¥104 to <1¥1011 ohms range.

In highly ESD-sensitive areas, air ionization often becomes a critical component to the neutralization system when devices cannot adequately be connected to ground or in the presence of insulating materials in the workspace. There are a variety of ionization technologies (see CleanRooms' online product guide at Cleanrooms.com)—AC high voltage, radioactive, DC high voltage and X-ray—that can be applied to control charges in a small area or for an entire room.

Support your layers with training

After the appropriate layers of ESD protection have been designed into the cleanroom operation, training of all personnel, from management to operators, is a key element of an effective protection program.

Line personnel must understand the proper use and importance of static control equipment and procedures such as grounding, wrist straps, garments and packaging. Management must understand and actively support the ESD protection program, including allocating funds and resources to implement and continuously improve the system.

Involvement in industry organizations such as the ESDA and Institute of Environmental Sciences and Technology (IEST; Rolling Meadows, IL) will provide access to expertise and the most recent ESD developments.

The benefit to your cleanroom business from these layers of ESD defense will include higher manufacturing yields, less rework and inventory, reduced overall costs, fewer field failures and warranty calls, increased product reliability and more repeat business resulting in greater profits. Return on the investment from effective ESD programs have been demonstrated to be in the range from 1,000 to 3,000 percent.7,8

Alan Learned, Ph.D, is research associate, R&D, Dupont Nonwovens in Richmond, VA. Learned has a B.Sc. in chemistry from Sterling College and a Ph.D. in organic chemistry from the University of Utah and is a member of the IEST. His areas of research/expertise include fiber and fabric engineering and fabric and garment functionality and application performance.

References:

  1. IEST-RP-CC022.2, "Electrostatic Charge in Cleanrooms and Other Controlled Environments," Institute of Environmental Sciences and Technology, 940 East Northwest Highway, Mount Prospect, Illinois.
  2. Smallwood, J., "Technical Report IEC61340-5-1 & 2: Protection of electronic devices from electrostatic phenomena", Southhampton, Hampshire, UK.
  3. Intel Technology Journal, "Semiconductor Technology and Manufacturing," Vol. 6, May, 2002.
  4. Solomon, P.M., IBM Journal of Research & Development, Vol. 46, May, 2002, p. 119.
  5. Dangelmayer, T., ESD Program Management, Second Edition 2001, Kluwer Academic Publishers, p. 99.
  6. ANSI/ESD S20.20-1999, "Protection of Electrical and Electronic Parts, Assemblies, and Equipment (Excluding Electrically Initiated Explosive Devices)," Electrostatic Discharge Association, 7900 Turin Road, Rome, NY, 1999.
  7. Pierce, R.J., "Static Control Pays," EOS/ESD Technology Europe Spring, 1990.
  8. Dangelmayer, T., ESD Program Management, Second Edition 2001, Kluwer Academic Publishers, p. 405.

Common ESD failure models
There are three common ESD failure models used by the electronics industry to represent and test ESD events.

The Human Body Model (HBM) was developed to simulate the action of a human body discharging accumulated static charge through a device to ground. HBM-type events can occur in cleanrooms, but with a well-designed ESD program including training, these can be minimized. HBM events in the field are expected to continue to be common.

The Machine Model (MM) simulates a machine discharging accumulated static charge through a device to ground. MM is primarily a more severe form of the HBM model.

The third model, the Charged-Device Model (CDM) simulates charging and discharging events that occur in production equipment and processes. CDM-type ESD events are expected to continue to increase and to describe the majority of ESD-related failure in the future.

CDM ESD events occur when there is metal-to-metal contact, such as a device sliding down improperly grounded rollers and hitting a metal surface. Another type of CDM ESD event can be caused by static induction, a process in which a neutral device is placed near a static charge and electrostatic potential is generated that can damage the device.

ITRS calls for increased attention to ESD
ESD events can be difficult to identify and undetected device damage is sure to cause customer dissatisfaction. We must give ESD proper attention to ensure customer satisfaction.

And as we look to the future of electronics developments, it's clear that ESD challenges will increase while the economic benefits of incorporating ESD precautions will increase in lock-step.

The International Technology Roadmap for Semiconductors (ITRS), which projects technology goals for chip and package characteristics through 2014, has been an accurate predictor of semiconductor technology development. The ITRS calls for a one-billion transistor chip to be in production by the year 2008 (as compared to a 4,000 transistor chip in 1970 and 170 million transistor high-performance chip in 2001).

Goals of a 10 billion transistor chip by 2010 have been published with step change technologies currently being demonstrating for 15-nm gate-length transistors, 130 nm process technology (can create circuitry wire widths that would require 1,000 side-by-side to equal the width of a human hair), 300 mm wafers and extreme ultraviolet (EUV) lithography that allows printing of lines smaller than 50 nm, and flash cell memory increases that will allow "wireless Internet on a chip."3

System-on-a-chip (SoC) concepts integrate logic, random access memory (RAM), RF, analog, and dynamic random access memory (DRAM) on the same chip for cluster computing and applications that blend computers inconspicuously into common household tools and appliances. New material systems of Ge, GaAs, and InP and silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) offer increased performance for the semiconductor devices.4

And while the performance benefits of these technologies are astounding in their speed, processing power and size, the increased chip density also causes a potentially dramatic increase in ESD sensitivity. As the gate oxide becomes thinner (<50 Å), breakdown voltages become lower.

The shallower junctions are more prone to degradation. Dielectrics become thinner and new materials with different melt properties increase failure potential. Narrower conductor lines become more susceptible to fusing. For example, a 1.0-micron technology has a Human Body Model (HBM) threshold of 4.5 kV, while at 0.1 micron the HBM threshold drops to 0.9 kV and the sensitivity to gate oxide damage that typically is caused by Charged Device Model (CDM) ESD can increase by as much as 20 times.5