Device Architecture

DEVICE ARCHITECTURE ARTICLES



Nanowire-based charge-trapping memory optimized by NIST, GMU

05/23/2011 

TEM of a Si nanowire is shown surrounded by a stack of thin dielectric layers. SOURCE: NISTThe National Institute of Standards and Technology (NIST) George Mason University (GMU) researchers are studying the optimal characteristics of silicon nanowires and dielectric stacks for charge-trapping memory.

3D integration: Bringing it home with supply-chain buy-in

05/19/2011 

A recurring theme at this year's Confab is that 3D integration shows tremendous promise, particularly with many fabless companies, yet many barriers remain -- and the first and biggest is preparing the supply chain.

Tighter chip densities tease out litho, metrology weaknesses, says Intel

05/19/2011 

Janice Golda, Intel, co-led a session at The ConFab 2011 on continued device scaling. EUV infrastructure will be a major topic, as well as transistor challenges. While lithography difficulties exist at tighter device densities, Golda reminds us that metrology obstacles must also be tackled.

Non-planar device scaling: SEMATECH talks TSV, SoC, SiP

05/19/2011 

The semiconductor industry is moving to 3D device structures, says Raj Jammy, SEMATECH, at The ConFab 2011, discussing TSV and system-in-package (SiP) opportunities and challenges. He also summarizes logic and memory roadmaps.

Trade-offs and infrastructure are keys to device scaling

05/18/2011 

Raj Jammy, VP of materials and emerging technologies at SEMATECH, covered a broad swath of CMOS scaling drivers, system and device trends, and infrastructure requirements.

Making progress with EUV

05/18/2011 

imec's An Steegen outlined the requirements to continue Moore's Law and new technologies being pursued to that end. Perhaps most important is lithography, where she provided an update on EUV tool productivity, resist benchmarking, and mask defect results.

Transistor phenomenon could revive clock speed advancement

05/13/2011 

A sample of the lanthanum aluminate-strontium titanate composite, which looks like a slab of thick glass, with thin electrodes deposited on top of it. SOURCE: MITMIT and University of Augsburg researchers discovered that layered insulators lanthanum aluminate and strontium titanate create a capacitance -- at room temperature -- that cannot be explained by existing physics. The discovery could create entirely new transistors that do not rely on silicon semiconductors.

CCD pioneer, Dr. Willard S. Boyle, dies at 86

05/13/2011 

Dr. Willard S. Boyle, along with George E. Smith, invented the charge coupled device (CCD) that, until recently, dominated the digital image capture market. Boyle and Smith developed the CCD some 4 decades ago at Bell Laboratories (NJ). The men were awarded the 2009 Nobel Prize in Physics for this work.

CMOS image sensors see growth beyond cellphones

05/11/2011 

Figure. CMOS vs CCD image sensor dollar volumes. Source: IC Insights May 2011.CMOS image sensors did not see the same strong rebound in 2010 that the semiconductor industry at large experienced. New momentum, driven by new system applications outside of camera phones and digital still cameras, could focus CMOS image sensors on growth from 2011 on, says IC Insights.

Day 2, 3 talks on process integration, reliability, 3Di

05/11/2011 

John Iacoponi, IITC 2011 co-chair, reviews Day 2-3 discussions at IITC/MAM, including interconnect reliability, BEOL memory, 3D integration, process integration, ultralow-k, and future-looking talks on graphene and carbon nanotubes.

Update from Japan: Energy policy under review, fabs recovery upset

05/10/2011 

Longtime semiconductor exec Takeshi Hattori continues his reporting on the aftermath of the massive Japanese earthquake and tsunami: Japan's reviewing its energy policy to deemphasize nuclear power, and updates on recovery efforts at Renesas, Toshiba, and Tohoku U.

RFaxis' pure-CMOS on-die coexistence filter reduces package size, current consumption

05/10/2011 

RFaxis released its patent-pending On-Die Coexistence Filter technology, designed to replace "bulky and expensive" stand-alone coexistence filters for cellular, mobile, and other devices.

IITC: Sneak-peek at Day 1 talks

05/09/2011 

John Iacoponi, IITC 2011 co-chair, reviews presentations and discussions on the first day of the event: three important aspects driving today's semiconductor business, and technical papers on packaging, photonics, low-k, and characterization.

Leading-edge processes, MEMS, Japan turnaround driving 2011 wafer demand

05/06/2011 

Total wafer demand will increase 11.2% to 185.3M wafers (200mm equivalent), with a number of factors driving growth above average rates, according to a recent Semico Research report.

Analysts' take: Intel's four trigate transistor triumphs

05/05/2011 

As a follow-up Intel's announcement of a new 22nm trigate transistor structure, we polled and tracked multiple industry watchers for their thoughts on the technology. Their key takeaways: Intel reasserts its manufacturing prowess, and could be setting up for plays in mobile and foundry.

SRC attacks 3DIC reliability, design tools with new effort

05/05/2011 

Semiconductor Research Corporation is leading an effort to address key roadblocks for wide-scale adoption of the emerging 3D ICs and systems. These new initiatives will address critical reliability and design tool issues and leverage partnership between researchers from universities and the semiconductor industry.

Intel readies 22nm leap, with trigates

05/05/2011 

Intel has taken the wraps off its next chip technology, a 22nm process utilizing a new 3D trigate architecture that promises faster speeds or big power savings, which will ramp to volume manufacturing later this year.

TSVs, beyond-CMOS top IITC-MAM "must see" lists for conference chairs

05/04/2011 

Cross-sectional TEM images of metal caps on 66nm wide Cu lines for three different processes: a) process A with 5nm-thick and full coverage; b) process B with <3nm-thick and partial coverage; c) process C with 8nm-thick and partial coverage; and d) a dark-field image along with the line direction with the metal cap "A."Three chairs of IITC-MAM, opening next week in Germany, share details on papers attendees won't want to miss. Among the hot-button technologies are through silicon via (TSV) integration, RC performance, carbon interconnects, and pushing traditional technologies farther (think lithography).

CMOS image sensor IDM orders multiple Camtek AOI systems

05/03/2011 

Camtek received a follow-on order for its new Gannet automatic optical inspection (AOI) system from a leading Asian integrated device manufacturer (IDM) for the application of CMOS image sensor inspection.

28nm node: It's not for everyone

05/02/2011 

"28nm is not a node for all," says Mahesh Tirupattur, EVP at Analog Bits and moderator of the 28nm challenges panel at this week's Semico Summit. Panelists will share what it takes to integrate 28nm right the first time, with examples like Apple's iPad hardware.




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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