12/17/2010 

At IEDM 2010, Renesas chief engineer Yoshihiro Hayashi shares details about the company's new logic IC-compatible eDRAM targeting system LSIs 28nm and below, including development of a special porous film for the interconnect layer to suppress metal contamination.

12/16/2010 

Michael A. Fury continues with observations from IEDM 2010, looking at 2nd-day papers on a 90nm CMOS image sensor; an 11nm planar multi-gate CMOS design with self-assembled gates; SiC/GaN power electronics for auto systems; an update on future memory technologies; and a transparent photosensor array with triple oxide TFTs as both switches and sensor elements.

12/16/2010 

Raj Jammy, SEMATECH, explains the details behind contact resistance reduction using dielectric dipole-mitigated Schottky barrier height (SBH) tuning on a FinFET source/drain. Reduction of the SBH by 100meV from the AlO_x/SiO₂ dipole results in a 10Ω-µm² reduction in specific contact resistivity and a 100Ω-µm reduction in FinFET source/drain resistance (R_S/D).

12/15/2010 

Dr. Phil Garrou looks at 3D IC technology discussions at IEDM 2010, including details of TSMC's integration of 3D into its advanced CMOS foundry processes, and a close examination of 3D-induced stresses.

12/15/2010 

Techcet's Michael A. Fury reports in-depth from sessions at IEDM 2010, looking at papers on NAND flash using airgaps, a lock-and-key method for 3D integration, RF performance of graphene FETs, and FET-built DNA biosensors.

12/14/2010 

SEMATECH's IEDM 6.2 paper demonstrated self-aligned III-V MOSFETs hetero-integrated on a 200mm substrate and fabricated with state-of-the-art industry standard silicon processing tools. Raj Jammy, SEMATECH VP, materials & emerging technologies, describes in detail the challenges that had to be overcome to complete the research.

12/14/2010 

Which transistor structures and materials will garner the most support at 16nm and below? In this podcast interview, Dean Freeman, VP of research, Gartner, provides his perspective on the various paths: FinFETS, tri-gates, fully-depleted SOI (FDSOI), Ge/III-V, bulk CMOS, and so on.

12/13/2010 

At IEDM, Semiconductor Research Corporation and researchers from Waseda University announced process and materials development  for precisely controlling both the amount and the position of channel dopants. The researchers say this advance should help extend the manufacturability of semiconductors beyond conventional doped-channel device technologies. The result is projected to enable near atomic-scale devices and single-dopant devices.

12/10/2010 

Diodes Incorporated (Nasdaq: DIOD) released its first device in its unique PowerDI5060 package, the DMP3010LPS 30V rated p-channel enhancement mode MOSFET.

12/09/2010 

A power outage at a Japanese power plant has put a big dent in Toshiba's NAND flash output, according to multiple reports, though industry watchers are mixed as to the ultimate market impact, and who might take advantage with key NAND consumer Apple.

12/09/2010 

Techcet's Michael A. Fury reviews the themes of keynote talks at this week's IEDM conference: challenges and opportunities for future silicon technology (particularly memory), energy efficiency enabled by power electronics, and the crossover of electronics and biotech.

12/08/2010 

Panasonic developed a new technique to increase the blocking voltage of gallium-nitride-based power switching transistor on silicon substrates. The blocking voltage of the Si substrate can be added to that of the GaN transistor by the new structure, which will enable the blocking voltage over 3000V.

12/07/2010 

Worldwide semiconductor sales were flat in October vs. September at ~$26M according to the SIA's latest monthly data, but are still on pace to meet the group's >32% growth rate for the year, assuming November and December are flat as well.

12/07/2010 

At this week's IEDM, IMEC and Panasonic reveal a new MEMS resonator with the industry's highest-recorded quality factor, thanks to two key process and manufacturing steps.

12/06/2010 

At this year's IEDM 2010, Intel is revealing a high-mobility Ge QWFET with ultrathin oxide thickness for low-power CMOS apps, the first demo of significantly superior mobility to strained-Si in a p-channel device.

12/02/2010 

Vishay Intertechnology Inc. (NYSE: VSH) has entered into a new five-year $450 million credit facility. The senior secured facility, which matures on December 1, 2015, replaces VSH's prior $250 million revolving credit facility, which was scheduled to mature on April 20, 2012.

12/02/2010 

At IEDM in San Francisco, CA, researchers from University of California at Berkeley and Texas Instruments (Dallas) will show that, among three common stressor techniques, MugFETs benefit the most from strained capping layers, also known as CESLs. Laura Peters, contributing editor, reports.

12/01/2010 

The latest semiannual forecast update from the World Semiconductor Trade Statistics (WSTS) sees 2010 as even better than expected in its midyear forecast six months ago, but going forward chip sales should be much less surprising. Key themes: memory's cooling off, MPUs are heating up, and the Americas lead the way.

12/01/2010 

The recent difficulties in semiconductor sales and the unusually rapidly declining IC price/performance index are slowing semiconductor equipment demand. Essentially, 2010 has been a 2-for-1 deal for both chips and equipment with two years of growth in one year, resulting in overcapacity and declining chip prices, says VLSI.

12/01/2010 

The consideration for the acquisition is approximately $38 million, comprising of approximately $17 million in cash and 1.8 million AOS's common shares. Prior to this acquisition, AOS held 43% equity stake in APM.