Device Architecture

DEVICE ARCHITECTURE ARTICLES



CMP for metal-gate integration in advanced CMOS transistors

11/01/2010  The needs of replacement metal gate HKMG process flows for 45nm node and below CMOS manufacturing are now being met with processes using consumables designed specifically for these steps. Paul Feeney, CMP Fellow, Cabot Microelectronics Corp., Aurora, Illinois, USA

Planar fully depleted SOI: the technological solution against variability

11/01/2010  FDSOI technology exhibits outstanding variability results, thanks to the use of an undoped channel, and to the good control of silicon film thickness already reached today on commercial SOI wafers. F. Andrieu, O. Weber, J. Mazurier, O. Faynot, CEA-Leti, Grenoble, France

IEDM preview: Multi-threshold-voltage Flexibility in FDSOI

10/27/2010 

Under the theme at this year's IEDM of better ways to generate, transmit, use, and save energy, a group of researchers from Europe will demonstrate low-Vt nMOS and pMOS workfunction-adjusted devices manufactured using TiN/TaAlN metal gates in ultrathin fully-depleted silicon-on-insulator (FDSOI) substrates.

RAM-memory-research-A-RAM-RERAM-MSDRAM-MELRAM projects

10/27/2010 

CNRS research on memory wafer fabWhile speculation abounds about what will be the next generation of memories and their applications, CNRS, a French government-funded research organization, has 4 new concepts of memories in 2010. The organization is actively recruiting collaborators on RE-RAM, A-RAM, MS-DRAM, and MELRAM memory technologies.

Vishay Siliconix Medical MOSFETs marks foray into implantable apps

10/25/2010 

Vishay Intertechnology Inc. (NYSE: VSH) released two devices in its first family of power MOSFETs built on an enhanced process flow with strict manufacturing process controls for implantable medical applications.

Ion implantation: Device process optimization for Nwell implant on CMOS 13?m

10/25/2010 

Ion implantation: Device process optimization for Nwell implant on CMOS 13umOver the years, undesirable process effects related to ion implantation have become well known: the like channeling effect, for example, and how to minimize it for 25μm and 13μm mature technology. Patrick Demarest, Altis Semiconductor, describes how a stable process can emerge in data mining analysis for low final test yield, and provides definitions for incidence, tilt and twist angles, and channeling effects.

IEDM Preview: CMOS imager works from light to night

10/22/2010 

At the upcoming IEDM conference in December, researchers from NoblePeak Vision will explain how they achieved the first large-scale integration of a single-crystal germanium photodiode into a silicon imager, creating a CMOS sensor that offers high-resolution night imaging under moonless conditions.

IEDM preview: IM Flash details 25nm NAND

10/18/2010 

Intel and Micron researchers will reveal the key process advances and electrical results behind their multilevel cell (MLC), 64Gb NAND flash memory technology at the upcoming International Electron Devices Meeting (IEDM) in December.

Memory growth drives Sonics to open Taiwan design center

10/15/2010 

Sonics added a design center in Taipei, Taiwan, to accommodate increasing demand for its line of memory subsystem solutions. Sonics' R&D efforts will focus on existing as well as future memory subsystem technologies to help SoC designers solve memory bottleneck challenges and cost-effectively increase memory bandwidth and DRAM efficiencies.

GaAs, epitaxial foundry services added at RFMD

10/12/2010 

RFMD added its GaAs technology to its foundry services portfolio and will begin providing a full suite of GaAs pHEMT technologies. RFMD also expanded its Foundry Services to deliver multiple molecular beam epitaxial (MBE) platforms, epitaxial characterization and epitaxial development structures.

Crocus MRAM begins integration into TowerJazz 13um CMOC foundry process

10/11/2010 

TowerJazz and Crocus Technology completed the first stage of integration of Crocus’ Thermally Assisted Switching (TAS)-based MRAM technology into TowerJazz’s 0.13-µm CMOS process. As a result of the collaboration, a special low temperature back-end process technology was developed.

austriamicrosystems extends beyond standard foundry offering into advanced packaging

10/07/2010 

austriamicrosystems Full Service Foundry introduced "More Than Silicon," a comprehensive service and technology package that goes beyond standard foundry services. Foundry customers receive access to leading-edge technology add-ons, advanced packaging services, and dedicated support engineers to enable first-time-right designs.

iSuppli trims forecast on soft demand, inventories

10/05/2010 

Just two months after beefing up its semiconductor sales forecast because of the sector's "roid rage," iSuppli has put those numbers on a cooldown rep, citing concern over end-user demand vs. inventories.

3D roadmaps begin to converge

10/04/2010 

Last month's SEMICON Taiwan 3D Technology Forum shed some insight into what several foundries, assembly houses and customers are thinking about the timing for 3D interposers and full 3D IC, reports Phil Garrou.

Tessera sues Sony, Renesas on IP use, UTAC-Taiwan on contract breach

10/04/2010 

Tessera Technologies (NASDAQ:TSRA) took 2 new legal actions via its semiconductor packaging subsidiary, Tessera Inc., against Sony and Renesas, claiming lapsed licensing of its packaging technology. Tessera also logged a complaint in US District Court against UTAC (Taiwan) for breach of contract. Tessera provides a status update on ongoing legal actions.

20nm fully depleted SOI process available via CEA-Leti and CMP

10/01/2010 

CEA-Leti and CMP (Circuits Multi Projets) announced the launch of an exploratory multi project wafers (MPW) initiative based on fully depleted silicon on insulator (FDSOI) 20nm process, opening the access of its 300mm infrastructure to the design community.

Picotest Signal Injectors improve regulator, power supply test accuracy

09/27/2010 

Picotest released a new family of Signal Injectors, or adapters, to improve voltage regulator, LDO, and power supply testing accuracy. Increased bandwidth and higher resolution measurements are enabled for PSRR, stability, crosstalk, reverse transfer, input impedance, Bode plots, and crosstalk tests along with non-invasive in-circuit testing (ICT) for load transients, stability and output impedance. Picotest released a new family of Signal Injectors, or adapters, to improve voltage regulator, LDO, and power supply testing accuracy. Increased bandwidth and higher resolution measurements are enabled for PSRR, stability, crosstalk, reverse transfer, input impedance, Bode plots, and crosstalk tests along with non-invasive ICT for load transients, stability and output impedance.

The end of DRAM manufacturing cost gains?

09/23/2010 

DRAM manufacturing costs are on the rise for the first time in four years, raising questions about production expenses in the memory industry, but things should improve in a few quarters, according to a new report from research firm iSuppli.

IC design project concludes on self-adaptive system on chip: Discoveries summarized

09/21/2010 

REALITY focused on the design and analysis of energy-efficient self-adaptive system-on-chips (SoCs). The tackled challenges include benchmarking the impact of the latest 32nm CMOS process manufacturing variability at all abstraction levels, from device to SoC level, while developing approaches to compensate their negative impact in the design of final products.

NOR Flash market through 2013: Asia Pacific leads the pack

09/15/2010 

Research and Markets added "Global NOR Flash Market 2009-2013" by Technavio Insights to their report offering. The Global NOR Flash Market 2009-2013 report forecasts the NOR Flash market to grow at a CAGR of 5.4%, with the Asia-Pacific and China (APAC) region witnessing highest growth rate.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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