Device Architecture

DEVICE ARCHITECTURE ARTICLES



IEDM news: Panasonic shows >10kV GaN power transistor

12/14/2007  December 14, 2007 - At this week's IEDM, Matsushita Electric Industrial Co. Ltd. said it has built a gallium nitride (GaN) power transistor on a sapphire substrate with ultrahigh breakdown voltage of 10,400V, more than 5X higher than the top mark for other such devices.

IEDM news: Fujitsu updates work on ReRAMs, multilayer interconnects

12/14/2007  December 14, 2007 - At this week's IEDM, Fujitsu discussed its recent progress in developing multilayer interconnect technology for logic LSI devices at and beyond the 32nm node, and its work with a new resistive RAM (ReRAM) memory as a possible alternative to flash for embedded applications.

SRC, Glasgow to research compound semis for 8nm features

12/13/2007  December 13, 2007 - The Semiconductor Research Corp. (SRC) and U. of Glasgow are partnering to identify "the best" p-channel material to scale MOSFET minimum feature sizes, including gate length, down to 8nm, possibly extending scaling for another 4-6 years beyond current projections.

Micron touts new 68nm 1Gb DDR2

12/13/2007  December 13, 2007 - Micron Technology says it has produced samples of a 1Gb DDR2 device using 68nm process technologies. Mass production is planned for early 2008, followed by DDR3 and other low-power DRAM products in 2H08.

Teradyne tests flash mettle with Nextest M&A

12/12/2007  December 12, 2007 - Teradyne and Nextest have agreed to a $325M acquisition that gives system-on-chip test provider Teradyne a big slice of the projected $700M flash memory tester market.

X-Fab licensing process tech to Brazil for first 150mm fab

12/12/2007  December 12, 2007 - German chipmaker X-Fab Silicon Foundries has agreed to license its 0.6-micron process technology ("XC06") to Brazil's CEITEC (Excellence Center for Advanced Electronic Technology), for use in CMOS semiconductor manufacturing in the country's 150mm prototype frontend wafer fab, slated to open in 3Q08.

Palomar Partners with Vision Manufacturing to Add PWB and SMT Services

12/11/2007  ; Palomar Technologies has announced a partnership with Vision Manufacturing Inc. (VMI) of Vista, CA. Through VMI, Palomar Microelectronics can offer printed wiring board (PWB) and surface mount technology (SMT) services for its customers to supplement the process development, prototyping, and low volume assembly services Palomar Microelectronics provides.

2007 IEDM: Darts hit elements all over the period table

12/11/2007  Over 1600 technologists are gathered in Washington, DC, to explore a wide range of innovative ideas at the 2007 International Electron Devices Meeting (IEDM). While current mainstream CMOS approaches, using strain engineering and metal/high-k dielectric gates, are covered extensively, a wide range of further out alternatives suggests that darts have been tossed at periodic table charts all over the world.

Interview: Advantest sees order recovery in mid-'08

12/11/2007  December 10, 2007 - In an interview with Japan's Nikkei daily, Advantest president Toshi Maruyama admits the company misjudged the timing of the DRAM price drought, but is optimistic that backend tool orders will pick up by next summer -- as long as midsize manufacturers get back in the game, and the US subprime mortgage debacle doesn't sour consumer spending habits.

Tessera's ITC complaint targets DRAM makers

12/11/2007  December 10, 2007 - Tessera Technologies has filed a new complaint with the US International Trade Commission (ITC) alleging unlawful importation and sale of certain small-format BGA semiconductor packages and products, including DRAM memory chips, memory modules, and the computer systems incorporating them.

IBM: We've made 32nm high-k "gate first" SRAMs

12/10/2007  December 10, 2007 - IBM says it has fabricated 32nm chips using a high-k/metal gate (gate-first) process in SRAM chips, which it says shrinks the chips size by up to 50%, and saves about 45% total power. The technology is expected to be available in 2H09.

Intel at IEDM: 45nm HK+MG, variation mitigation, Moore's Law beyond 2015

12/10/2007  Intel execs revealed highlights from select papers the company will be presenting at IEDM, including some details about its 45nm HK+MG transistors that incorporate a redistribution layer as part of a 9-layer copper interconnect. Also featured is the company's success in mitigating process variation to the extent that results in variation at 45nm is comparable to that achieved at 130nm. Additionally, quantum well FETs may be ready at ~2015 to extend Moore's Law scaling.

Analyst: 2008 capex down 5%-13%, DRAM firms cinch belts

12/07/2007  December 7, 2008 - Chip manufacturers are getting serious about buckling down on their capital spending, as profits have just about reached their "pain threshold," and the resulting belt-tightening will "shake the foundation of the IC industry," according to analyst firm IC Insights.

Successful MEDEA+ collaboration to continue under CATRENE

12/07/2007  This year's MEDEA+ annual forum in Budapest, Hungary (Nov. 26-28) reviewed final projects for the eight-year pan-European collaborate program for microelectronics R&D, set to expire in 2008 after overseeing three generations of CMOS technology and making the European industry a world leader in such sectors as automotive electronics, smart card technology, and image sensing.

Reports: Hynix prepping 48nm NAND ramp

12/06/2007  December 6, 2007 - Hynix Semiconductor expects to start mass production of 48nm-based NAND flash in 1Q08, which would give it a brief headstart on rivals Samsung and Toshiba, according to local media reports.

Hitachi Chemical hiking CMP slurry output

12/06/2007  December 5, 2007 - Hitachi Chemical plans to boost its production capacity for CMP slurry by 50% to 15,000 tons/year by next June, its second upgrade in the past year, according to the Nikkei Business Daily.

NXP sells off Crolles2 tools

12/05/2007  December 5, 2007 - NXP Semiconductors says it has sold off equipment from its participation in the Crolles2 partnership, mainly used for R&D and pilot manufacturing, to an undisclosed buyer for an undisclosed price. Ownership will be transferred in two stages over the next six months.

IMEC at IEDM: PVD for workfunction metals going forward?

12/04/2007  Researchers at IMEC gave WaferNEWS a preview of the group's papers to be presented at next week's IEDM 2007 conference in Washington, DC. Topics include PVD used for workfunction electrode metal in FinFETs; interactions between a capping layer, host dielectric, and workfunction metal that impacts threshold voltage; and using laser annealing in (gate-first) HK+MG devices to achieve gate length scaling with no loss in drive current.

SVTC, SEMATECH's ATDF merge to expand R&D capabilities

12/04/2007  December 4, 2007 - Months after significant reorgs on both sides, the SVTC (nee the Silicon Valley Technology Center) and SEMATECH's R&D foundry subsidiary Advanced Technology Development Facility (ATDF) in Austin, TX, are merging to expand their ability to offer an alternative to dedicated R&D fabs or shared development/production operations, months after both sides took steps earlier this year to reorganize and expand.

Tessera Announces Guest Speakers for Tokyo Technology Symposium

12/04/2007  ; Tessera has announced that executives from Hewlett Packard, Intel, Nokia and Toshiba will be guest speakers at the fourth annual Tessera Technology Symposium in Tokyo, Japan, tomorrow. The theme of this year's conference is "Driving the Mobile Revolution."




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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