Managing process variations

03/01/2013

Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions

Process variations are becoming one of the biggest challenges that both process development engineers and circuit designers must deal with in advanced process nodes. The increased random variations and layout-dependent effects inevitably and significantly impact the yield of a chip. Therefore, these process effects must be physically understood and accurately modeled up front in SPICE models that can be used later by the circuit designers during various circuit design stages, including simulation and verification.

To reduce risks for low-yield wafer manufacturing and design re-spins or even re-design, accurate yield prediction and realistic design optimization between performance and yield are urgently needed. The keys here are the accurate statistical models and useful design tools with high prediction accuracy and superior simulation performance.

Traditionally, engineers selectively run process, voltage and temperature (PVT) corner analysis and Monte Carlo analysis. Unfortunately, the process information given by the foundry models are sometimes either too conservative or too optimistic, and the foundry models may be used inappropriately or incorrectly on an application-specific basis. Compounding the problem are selective corner models and Monte Carlo analysis approaches often employed by circuit designers may give limited information, giving them low confidence on the yield prediction and design optimization. As a result, the overall design efforts may lead to loose conclusions. What's worse, the information and value given to circuit designers are, in fact, limited.

In another scenario, the variation model in the SPICE model library of a process design kit (PDK) is the only channel where designers can understand the complexity of variations and its relation to design. Its accuracy, completeness and quality can impact the final simulation and analysis results and confidence level. Having good model knowledge and properly using and applying it in the design flow offers increasing value, not to mention that improper usage of models may lead to deviated results.

Since the lack of integration can lead to a loose integration to simulators, one remedy would be to enhance the link between design and manufacturing by integrating modeling, simulation and statistical analysis software tools. A set of elements for yield analysis can make the yield analysis more reliable and realistic.

There are three key components for handling process variations for circuit designs, i.e., accurate SPICE models considering process variations, a fast and reliable statistical simulation engine and hardware-validated sampling technologies. Performance can be improved and the license cost can be reduced immediately with an integrated SPICE engine instead of using an external engine. Having none of those components can lead to a loss in accuracy and degradation in simulation performance as well.

An integrated flow could enable designers to better use foundry corner models or help them re-generate corners, representative of the applications to improve efficiency and confidence levels for PVT analysis. Another analysis tool needed for yield prediction is Monte Carlo, which requires good statistical models. An integrated SPICE engine and hardware validated sampling technologies help designers here as well because they make the DFY more practical and faster, yet accurate because SPICE accuracy is preserved and sampling technologies are validated.

Managing process variations is something the semiconductor industry needs to pay more attention to, while the design community and foundries need to work more collaboratively to expand on the foundry-fabless model. The answer could come by more closely linking design and manufacturing with a rich software suite of SPICE modeling, circuit simulation and statistical analysis tools.

Solid State Technology | Volume 56 | Issue 2 | February | 2013