MAPPER Lithography tech resolves 22nm

03/01/2012

Research institute CEA-Leti shows "significant progress" with the MAPPER Lithography massively parallel direct write technology, resolving 22nm dense lines and spaces and 22nm dense contact holes in positive chemically amplified resist. The maskless lithography tech meets semiconductor industry requirements for 14nm and 10nm logic nodes.

The progress was reported in the 5th Operational Review of the IMAGINE program hosted by CEA-Leti this January. The industry
esearch multi-partner program includes leading semiconductor manufacturers TSMC and STMicroelectronics and suppliers like Nissan Chemical, TOK, Dow, JSR Micro, Synopsys, Mentor Graphics, Sokudo, Tel and Aselta. It was formed to evaluate a maskless lithography infrastructure, using multiple e-beam lithography from MAPPER.

CEA-Leti and Mapper will continue the IMAGINE program for 3 more years, through the installation of one of MAPPER's first pre-production maskless lithography Matrix systems at CEA-Leti. MAPPER's pre-alpha platform has been installed in CEA-Leti's cleanroom since mid-2009.

"In 2012, MAPPER will complete its Matrix pre-production platform," said Bert Jan Kampherbeek, MAPPER CEO, adding that the tool's initial 1 wafer per hour (WPH) throughput will be scaled up to 10 WPH. ???M.C.

Solid State Technology, Volume 55, Issue 2, March 2012

More Solid State Technology Current Issue Articles

More Solid State Technology Archives Issue Articles