Technical forecast: 22nm devices


To understand the challenges associated with the industry's move to 22nm and smaller geometries, we asked leading industry experts to give us their perspectives on what we can expect. A collection of excerpts is provided here. For their full comments, head to:

Process technology challenges at 22nm

Dean Freeman, Research VP, Gartner.

The industry will see two different types of devices ramping in 2012: second generation 2xnm NAND flash, and Intel's 22nm microprocessors. In 2012 Gartner expects 22nn technology to account for 24.8 MSI per quarter of the total industry capacity. This accounts for less than 1% of the total capacity. Each of these technologies presents different challenges to manufacture and yield.


3D integration key to 22nm devices

Paul Lindner, Executive Technology Director, EV Group.

In the near future, we expect to see the most complex and competitive combinations of devices (e.g., logic combined with DRAM, Flash memory, CPU and GPU) being the most aggressive, both in adopting 3D integration and in heavily pushing further scaling. At the 22nm node, we also expect to see mobile, low-power and system-on-chip (SoC) applications implementing planar fully depleted silicon-on-insulator (FD SOI)-based transistors.

Mask-wafer double simulation: a new requirement

Aki Fujimura, CEO, D2S, Inc.

At the 20nm process node and beyond, multiple masks???each with complex mask shapes???are needed to achieve sufficient process window in the wafer for the critical layers. The complex shapes are created by optical proximity correction (OPC) adding a large number of sub-resolution assist features (SRAFs) and main features requiring complex contours.


Co-design, closer cooperation needed at 22nm

E. Jan Vardaman, TechSearch International, Inc.

As the semiconductor industry moves into the 22nm silicon technology node, device fabrication is not the only challenge that the industry will face. According to the International Technology Roadmap for Semiconductors (ITRS), a porous ultralow-k material will replace the traditional silicon dioxide. Stresses within the die must be controlled not only during the device fabrication process, but also during the packaging and assembly process.

Deposition technologies a key pathway for both planar and 3D devices

Mohith Verghese, Technical Product Manager, Thermal Products Business Unit, ASM America.

While the introduction of the first 3D (tri-gate) based microprocessor in production is anticipated at the 22nm node, the majority of semiconductor manufacturers will focus on planar replacement gate technology. Scaled high-k based gate dielectrics are considered absolute for this node, with physical thicknesses of the deposited materials approaching 10?? for the most aggressive high-performance applications.

Gate last approach to become the norm

Art Zafiropoulo, Chairman & CEO, Ultratech, Inc.

Last year, the hot topic was whether manufacturing would move to metal gate first or metal gate last. Today, this is still a hot topic, although I would say that everyone is going to use a gate last approach at 20nm. Currently 22nm is in production at Intel who is the first company to implement gate last, but others such as IBM and foundries like TSMC will also use it for 20nm manufacturing. I believe that 20nm manufacturing will be very difficult, and if this occurs, it will extend the period for 28nm. Possibly a mid-node may be developed or a "loose 20nm structure," because of the difficulty in obtaining acceptable yields. Essentially, we are at 28nm now and using gate first or metal gate last, but the industry will shift to a 20nm metal gate last approach, exclusively.

Defects will be key to CMP at 22nm

Michael A. Fury, PhD, Director & Senior Materials Analyst, Techcet Group, Del Mar, CA USA

Defect control at 22nm is a critical focus for CMP. Slurry manufacturers have worked hard to deliver stable suspensions that resist agglomeration in manufacturing, storage and shipment. Metrology suppliers have developed the ability to measure particle size distribution offline in undiluted slurry samples, emphasizing the large particle tail associated with scratch defects.

SMO and DPT to drive 20nm mask technology

Franklin Kalk, CTO, Toppan Photomasks.

With the first 20nm test chips coming out now, the 20nm mask production toolkit and materials have been selected and installed at the leading mask houses, and the 20nm mask process has been developed. The task for 2012 is to improve mask yield and cycle time before volume wafer manufacturing begins.


First order effects now the focus at 22nm

Howard Ko, SVP and GM, Silicon Engineering Group, Synopsys, Inc.

3D process and device simulation (TCAD) is now required as a way to guide and optimize the fabrication process. An important example of the need for 3-D TCAD simulation is in the process optimization of SRAM cells where stress and doping proximity effects require that all transistors comprising the SRAM be simulated in a single structure. This type of TCAD simulation has only become possible in the past year, with advances in 3-D structure generation, mesh generation and parallel algorithms.

Solid State Technology, Volume 55, Issue 1, January 2012

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