Researchers: SiOx OK for sub-10nm memory switch
11/01/2010
Researchers at Rice U. say that a new switching memory they built with electrically manipulated 10nm graphite strips doesn't actually need the graphite—good ol' reliable silicon oxide will do just fine.
Last year a team led by Rice prof. James Tour showed that electrical current could break and reconnect graphite strips, creating a memory bit. Now, grad student Jun Yao shows in a Nano Letters paper that the same thing can be achieved with silicon oxide between semiconducting sheets of polycrystalline silicon (as top/bottom electrodes); applying a charge forms a chain of nanosized silicon crystals—as small as 5nm—which can be repeatedly broken and reconnected by varying the voltage. As a proof of concept, he cut a carbon nanotube to localize the switching site, sliced out a thin piece of silicon oxide with focused ion beam, and identified a nanoscale silicon pathway under a transmission electron microscope.
Silicon oxide switches or memory locations require only two terminals, not three (flash memory) because the device doesn't have to hold a charge. It also can be stacked in 3D arrays (which is the direction memory is going) and would be compatible with conventional CMOS manufacturing technology. And while there are questions about the future of conventional memory below 2Xnm, "our technique is perfectly suited for sub-10nm circuits," Tour said in a statement. These SiOx circuits offer similar specs as the original graphite device: high on-off ratios, "excellent" endurance, and <100ns switching. They're also radiation-resistant, so they're also suitable for defense/aerospace radiation-hardened applications.
Austin design firm Privatran is bench-testing one of these silicon-oxide chips with 1000 memory elements, in work supported by a number of federal groups (NSF and the science arms of the Army, Air Force, and Navy). And a Rice spinoff company, NuPGA, is using vertical silicon oxide embedded in vias for rewritable gate array designs. — J.M.
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