Forging a TSV supply chain in a consolidated market
10/05/2010
Consolidation has been a mega-trend in the chipmaking world in recent decades. Dozens of EDA companies have been started and then acquired by the biggest two or three firms. Where there were once a half-dozen leading-edge lithography companies, now there are two – about the same number of leading players as most sectors of the equipment market.
This trend towards fewer, larger suppliers was predicted by many observers. It's a function of the maturation of the semiconductor industry, as well as formidable barriers to entry into it. Among these barriers are long sales cycles (it can easily take five years for a tool to go from initial design to real revenue), the need for global support and service, and the very limited number of potential customers.
From a top-level business perspective, it's worked out reasonably well. Chipmakers are designing and producing chips, equipment companies are starting to sell equipment again, and iPhones and DVRs are flowing nicely.
But from a more front-line perspective, there is cause for concern. Take the example of through-silicon vias (TSVs). This emerging technology is widely accepted as a basic enabler for current and future device generations, and also for the industry's advance into the "More Than Moore" space, where electronic devices will go beyond raw computing power to incorporate sensors, wireless networking, and battery-free power.
If you're a well-established supplier of chipmaking equipment or design software, you certainly want to play in the TSV market – but you want to do it in the way that's most beneficial to your company's bottom line. Very often, the best risk-reward combination is to adapt existing technology for a new application, rather than starting with a clean sheet of paper and identifying the best approach. As the risk of competition from startups decreases, the rewards of keeping R&D investments low increase. This is what we're seeing in the TSV sector – and it's starting to have negative effects on the industry's ability to adopt TSV technology.
Today, the supply chain is trailing ITRS expectations for TSVs. While it's possible to produce TSVs with an aspect ratio of greater than 20:1, circuit designers, always mindful of device manufacturability and cost, are limiting their designs to ratios of less than 10:1 to maintain compatibility with existing dry deposition processes.
Common sense tells us that device packaging should be relatively inexpensive, compared to front-end processing. But the available equipment for TSV production is very pricey because it was designed for dual damascene or MEMS applications, and there are insufficient incentives for the existing equipment leaders to redesign the equipment or lower its cost.
There are historic parallels to this issue, particularly bumping and wafer-level packaging. For years, wafer bumping was seen as a high-benefit solution for wafer-level packaging, but a lack of infrastructure was partly to blame for its slow adoption by offshore assembly and test houses. They couldn't afford the equipment that IDMs were using for bumping. Smaller equipment makers, seeing the opportunity, eventually stepped in and provided that missing link in the supply chain with lower-priced deposition tools.
Something along these lines will happen with TSVs; the free market has a way of reconciling these mismatches. Yes, it takes more time in a highly consolidated market with steep barriers to entry. But that slowness creates ever-increasing opportunities for the packaging suppliers who want to be the first to offer high-aspect ratio TSV technology, and the suppliers who can help make it economically practical.
Steve Lerner is CEO, Alchimer S.A., Massy, France, [email protected].
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