Toshiba's 25nm trial ups ante for NAND scaling, next-gen litho

06/01/2010

Toshiba is prepping a ¥15B (US $157M) investment in a <25nm NAND flash test line, eyeing mass production in 2012, a move that not only tightens the NAND flash scaling wars, but also could narrow the insertion point for a next-generation lithography set.

Toshiba's announcement ups the ante in the memory scaling race. The company's current NAND flash output is 43nm and 32nm. Earlier this year, IM Flash (the Intel/Micron JV) showed off its new 25nm NAND chip slated to ramp production in 2Q10.

Gartner research execs Dean Freeman and Joseph Unsworth offered a snapshot of NAND vendors' scaling plans. IM Flash has "about a six-month lead" in the scaling race, and all vendors quickly followed IMFT's February 2010 announcement with their own public updates. "It appears that we will have 25nmn in NAND at IM flash, Samsung, Toshiba and potentially Hynix before year-end in production," Freeman noted, though it's hard to quantify just what levels of "production" will be achieved. Unsworth doubts much will truly happen at production levels in the near-term. "Announcements are nice, but mass production at the most aggressive nodes in the semiconductor industry is another thing," he told SST.

Aside from handicapping the NAND flash scaling race, Toshiba's announcement also spotlights the potential entry point of next-generation lithography (in this case, EUV) into manufacturing. For the line at Toshiba's fourth NAND flash memory fab in Yokkaichi, Mie Prefecture, the company reportedly is bringing in an extreme-ultraviolet (EUV) lithography tool from ASML. The goal is that once "progress has been made" in the EUV work to get it to mass production, Toshiba's newest fifth fab at Yokkaichi will be outfitted for the technology "in the lower 20s" of process nodes, the paper says.

Toshiba reportedly aims to start 2Xnm production in 2H10, but has not identified specifically what that "X" number will be. The company is said to be "in talks" with ASML "on the possible purchase" of an EUV prototype tool; the local Nikkei daily reports that Toshiba has already ordered one.

Toshiba's evaluation of next-gen lithography options has included use of imprint technology, as well as rumors of "an EUV tool hidden somewhere," according to Freeman. But he thinks it is much more likely they will use immersion at 25nm, as did IM Flash with its 25nm devices. Throughput for one pass using immersion litho is 150 wafers/hour, including all the double-patterning steps and "other tricks of the trade to get the needed dimensions," he pointed out. EUV, meanwhile, is "maybe 10 wph or more likely 10 wafers per day" restricted by current source/laser capabilities. "So even with double-pass, the two etch steps, and the deposition steps required, you are probably still ahead of the game using immersion and double patterning over EUV."

The insertion point of EUV is still up for debate. At last summer's SEMICON West, ASML exec Bert Koek acknowledged that immersion lithography could be prolonged for NAND flash to 25nm and even 20nm, using spacers and 1.35NA. More recently, in an SST exclusive article, SEMATECH's Stefan Wurm suggested that both NAND flash and DRAM could move to EUV before the 22nm half-pitch—probably 27nm/25nm—and that tools would be ready to support pilot production in 2011 and volumes in 2013.

Nevertheless, Toshiba may be gaining an edge by learning the technology now on a pilot line. "When the EUV tools become ready they may have an advantage as they have worked out the bugs with resists, masks, and the process difficulties," Freeman notes. — J.M.

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