The second wave of 3D packaging technology: PoP

06/01/2010

Executive Overview Package on package (PoP) technology is the second wave of 3D packaging technology. It was developed to address the need for a more efficient packaging technology alternative. PoP enabled the integration of logic and memory chips on the same package form factor without the logistics and business-related issues involved with a logic-memory stacked die package alternative [1].

Mario A. Bolanos, Texas Instruments Inc., Dallas, Texas USA

The continued growth of consumer and portable electronics products has driven the need for new packaging technologies that enable reduced form factor and miniaturization. Based on the ability to deliver these attributes, new packaging technologies such as chip scale package (CSP) and wafer level chip scale package (WL-CSP) [1] have experienced strong growth. There is also high demand for innovations that exploit integration of multi components on the same package utilizing the third dimension (3D) to address the needs of these applications.

The evolution of 3D packaging technology has occurred in phases. The first wave emerged when multiple chips were stacked within the same package. Its initial growth and success came from the need to stack several memory devices in the same package, mostly to support increased demand for memory-rich requirements in mobile phones and portable electronics.

The second wave of 3D packaging is package-on-package (PoP). This article describes the PoP key features and challenges such as package warpage control issues during reflow process. It explains how this problem is compounded as new requirements are included in PoPs, such as reductions in total package thickness, higher level of die stacking on the bottom logic package, higher levels of density and pin count, and reductions of BGA pitch in both bottom and top package. Solutions to address these issues are also proposed [1].

Evolution in packaging technology

Figure 1 explains the transition from single die packages to multiple die packages and the impact to miniaturization and integration [2].

Figure 1. Packaging miniaturization and integration evolution.

Integration strategies have enabled further advancements in miniaturization of packaging technology. Additional innovations that exploit the third dimension (3D), such as through silicon vias (TSV) will provide an alternative interconnect method to stack chips on top of each other or to create SoCs with heterogeneous technologies, which ultimately may evolve into the third wave of 3D packaging and the full emergence of mega-integration era [2].

First wave of 3D packaging: stacked die packages

There are many potential package configurations with stacked dies. Some have multiple dies of different size, stacked on top of each other in a pyramid type of format. Other configurations use the same size dies stacked on top of each other (Figs. 2 and 3) [2]. Additionally, there are stacking alternatives that involve different die sizes that require over-hang between top die and bottom die. In all cases, die thinning, wire bonding and flip chip, together with die spacers and film die attach are some of the key enabling technologies for this type of packages. The need to support increased demand for memory-rich requirements in mobile phones and portable electronics drove initial growth and success of stacked die packages and the technology's ability to stack several memory devices in the same package.

Figure 2. Pyramid stacked die package.

There are also some products that require logic chips to be stacked with memory chips; however, these products did not achieve the same success as stacked memory chips. It is important to understand, however, that this challenge was not necessarily technical, but a result of logistics and the supply chain business model.

Figure 3. Same die size plus pyramid stacked die package.

To explain further, not all logic chip suppliers have memory chips in their product portfolio, which required complex procurement arrangements with memory chip suppliers that included assurance of quality, electrical testing and known good die. This challenge also created a lack of sourcing flexibility for commoditized memory chips in some cases. Lack of adequate chip-package co-design tools also impacted the ability to ramp products to market at the right time. The end result was increased product cost and time-to-market constraints in a market segment that cannot tolerate product introduction delays.

The need to address these issues, when integrating logic and memory devices in the same package, led to the development of a new solution, package on package (PoP) technology [2].

Second wave of 3D packaging: PoP

PoP technology emerged from the need to develop a more efficient packaging technology to integrate logic chips and memory chips on the same package form factor without having to deal with the logistics and business-related issues involved with a logic-memory stacked die package alternative. Texas Instruments was instrumental in developing PoP technology and has had PoP in volume production for at least five years.

In terms of structure, the bottom package is used for the logic chips, that could be a single chip package or a combination of a few logic chips, using mostly wire bonding to interconnect the chip to the substrate, but more recently flip chip is also being used. This package could handle the specific I/O and high pin count requirements of logic product including fine pitch ball grid array (BGA) second level interconnect to the system board if needed. The form factor of the bottom logic package follows JEDEC standards that basically secures that the form factor of the total package, including the one on top will meet JEDEC package body size and BGA pitch, just like any other single chip package (Fig. 4) [3].

Figure 4. a) Package on package (PoP) – one die on the bottom package, and b) Package on package (PoP) – two dies stacked on the bottom package.

The top package is reserved for memory chips, and in most cases it has multiple memory chips stacked depending on the product requirement. This set up enables a known good die alternative for the stacked die memory package because it can be fully tested by memory suppliers before integration with the bottom logic package.

The connection between the top and bottom packages is done to an array of pads located on the bottom package's periphery using standard surface mount assembly flow and a single solder reflow process step that takes place simultaneously with assembly of the bottom package to the system board. This is possible because the stacked die memory package typically has very low pin count that can be accommodated in the periphery of the bottom package. One of the main requirements is to prevent any mold compound or under fill contamination on the area assigned to peripheral interconnect pads on the bottom package. Otherwise there is a risk for surface mount assembly yield losses when connecting the top package with the bottom package.

PoP has been very successful in the market, achieving very high growth rates. But prior to its growth, there were issues such as package warpage control issues during reflow process to overcome. Tight process control is required to maintain very high surface mount assembly yield when connecting the bottom package to the system board.

There has been a lot of work in the industry aimed at optimizing the bill of materials used to construct these packages in order to minimize warpage. Surface mount assembly technology (or surface mount technology, SMT) was an initial concern for this package technology, but is now being practiced worldwide as a standard process in the contract manufacturing industry and major original equipment manufacturers (OEM).

This problem will be compounded as new requirements are included in PoPs such as reductions in total package thickness, higher level of die stacking on the bottom logic package, higher levels of density and pin count, reductions of BGA pitch in both bottom and top package.

Some of the alternatives being considered to address warpage control issues include thinner dies, thinner substrates, thin film die attach, carefully designed materials with the right material properties, thinner mold caps, and flip chip interconnect in order to facilitate low interconnect stand off between chip and substrate. Research and development of all the variables that contribute to package warpage and SMT assembly success continue to improve the performance of PoP [4].

Conclusion

The semiconductor industry has benefited greatly from growth and success of consumer and portable electronics products. Advanced packaging technology with stacking, integration and 3D technologies has driven the high levels of integration and miniaturization that the market required. PoP, together with wafer scale package and quad flat no lead package (QFN), have been the industry's most successful packages during the last decade, and their success will extend into this decade.

Figure 5. 3D packaging technology evolution.

The industry is in the middle of the 3D packaging technology era, and probably at the peak of the second wave of 3D packaging technology era (PoP) as it continues to develop and adopt packaging technology evolving from the early phases of the third wave of 3D packaging technology (TSVs) (Fig. 5).

References

1. Mario A. Bolanos, "Power Integrity Analysis and Management for Integrated Circuits," Ed. Raj Nair and Donald Bennett (ISBN 0137011229), Pearson Education (Prentice Hall Professional), Ch. 10, p. 1 (2010).

2. Ibid., p. 2.

3. Ibid., p. 3.

4. Ibid., p. 4.

Biography

Mario A. Bolanos received his BSEE and BSBA from Jesuit College (UCA), El Salvador, and EMBA from U. of Texas at Dallas and is the manager of strategic packaging research and external collaboration at Texas Instruments, Inc., 13536 TI Boulevard, MS940, Dallas, Texas, 75243; ph.: 972-995-7666; email  [email protected].

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