Inside the SOI Consortium's IP program

05/01/2010

The SOI Industry Consortium and several partners are launching a new "Ready for SOI Technology" program to broaden access to and encourage adoption of silicon-on-insulator technology, which can provide substantial improvements in chip performance and power requirements vs. bulk Si.

The program's goal is to make available design building blocks to chip designers for new applications such as mobile and consumer products. "The vision for the program is to make the ecosystem visible to designers—to reach out and get the same level of support as they get with bulk IP," explained Jeff Wolf, director of membership development for the SOI consortium and project lead for the "Ready for SOI" program. More specifically, the project addresses one of the key messages gleaned from users: What would it take to adopt SOI? "One was lack of IP for SOI," he said. Formation of this IP program directly addresses this issue "and takes it off the table."

To that end, a "microsite" is now hosted on ChipEstimate.com to help chip designers gain access to those design blocks. The available IP in this program focuses on physical IP, which is typically more difficult to port to SOI than synthesizable IP using industry-standard tools, Wolf pointed out. (Cadence also hosted a "SOI Jump Start Training" event on April 28, which has been recorded as a Webcast.) Key technology partners include IBM, ARM, Boeing (some of its IP targets a Honeywell process), Cadence, and Synopsys. A quick scan of the SOI portal shows about four dozen different IP that are available to port to SOI.

Initially the SOI IP focuses on IBM's 45nm foundry process, since 45nm is mainstream for current foundry sales, Wolf noted, but the goal is to expand both backward (65nm and 90nm) and forward (32nm). Last fall IBM prototyped a 32nm SOI chip and ARM, in fact, is working on SOI at the 22nm node, he pointed out. (Last fall ARM demo'd a test chip based on its 1176 processor using IBM's 45nm SOI process, with no prior SOI knowledge and using the same resources/timeline as a bulk design; more info on those 1176-on-SOI results are at www.soiconsortium.org/technology-corner/).

Included among the IP is IBM's eDRAM, tipped in late 2009, which offers potential for density and performance improvements. Horatio Mendez, executive director of the SOI Industry Consortium, noted that inclusion of IBM's eDRAM is key to enabling designs for applications such as data streaming (with stiff requirements for bandwidth capabilities and memory) and consumer applications, e.g., digital TV. These are "real-life applications—content that people can be using right away," he said.

Going forward, Mendez and Wolf say they want the program to expand the SOI ecosystem in two key directions: more IP providers, and more foundry support. GlobalFoundries and Freescale (both members of the IBM semiconductor technology alliance) build on SOI, and others have built prototypes—"virtually everyone has tried to work with it, but it's a business decision on how to market it," Wolf noted. Standard-space IP (e.g., bus interfaces) for SOI is expected to emerge over time, following the trend of how general IP has been developed, he added.—J.M.

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