ISSCC: 3D integration panel, IMEC's low-cost TSV
04/01/2010
A forum on silicon 3D integration at this year's IEEE International Solid-State Circuits Conference 2010 (ISSCC, Feb. 7-11, San Francisco, CA) brought together 3D integration technologies including system-in-package, through-silicon via (TSV), and contactless chip-to-chip communication, with an eye toward various components (SDRAM, flash, SoC, sensors, etc.) and applications (imagers, smart phones, solid-state drives, etc.).
Among the takeaways, as reported by IMEC's Pol Marchal, senior research in 3D integration:
- 3D technology is reaching maturity, but the design community still must pathfind opportunities; a "minimum hurdle" needs to be taken—most likely in memory or a mobile application where improved formfactor and power reductions by reengineering the DRAM interface "make lots of sense." Thermal challenges are also less.
- Reliability, especially in chip-package interation, is also a key concern for 3D. The different materials in the stack, bumps, underfill materials, and thin silicon dies with extreme low-k BEOL narrow design windows. (IMEC is active in this field with R&D and characterization through test chips, working with partners to put in place solutions for reliable systems, Marchal notes.)
Marchal et al. from IMEC had a separate presentation (paper 7.8) in which they offered ideas on design considerations for low-cost 3D through-silicon via (TSV) technologies, enabling applications such as logic-on-logic, DRAM-on-logic, and RF-on-logic. The TSVs were fabricated (5μm dia., 10μm minimum pitch) in 200mm/130nmCMOS logic with Cu/SiO2 BEOL; after etching the TSVs, an isolation layer was deposited followed by Cu metallization and then standard BEOL process.
The wafers were thinned to ~25μm and next TSVs exposed to height ~700nm, wafers were diced and stacked face-up on a regular thickness landing wafer win a die-to-wafer approach, reducing cycle time (by parallel processing of Cu-Cu thermocompression) and reducing overall cost since the die-to-wafer configuration enables pre-stacking selection of known good die.
Among findings after examining TSV formation and testing:
- Models and tools to design for TSV impact on devices can avoid large keep-out areas (in which no devices are placed) and keep down costs.
- Adding BEOL structures such as vias and serpentine wires next to/on top of TSVs help detect reliability problems.
- Unless power dissipation is managed across the tiers in a 3D stack, hot spots may occur (due to reduced thermal spreading and poorly conductive adhesives). Power dissipation was shown to be ~3× higher max temperature increase than 2D, requiring thermal-aware floorplanning to avoid thermal problems in the stack.
- Protecting TSVs from ESD would increase the footprint of 3D connections and thus cost—but in this presented technology, no ESD was required.
- Substrate noise isolation between stacked tiers was superior vs. 2D, seen as beneficial for mixed-signal and RF applications.
- Additional challenges include design-for-test and packaging of the 3D chip stacks, as well as further reliability testing.
Meanwhile, Intel presented a handful of papers with the emphasis on its 32nm "Westmere" processors, but two of them also crossed over into the packaging arena. Paper 8.1 described a chip-to-chip interface for future components (processors, memory, and peripherals) featuring a dense interconnect topology that promises 10× better power efficiency in data chip-to-chip than what's available today. Two components are on packages with interconnect between them, explained Randy Mooney, Intel Fellow and director of Intel Labs' I/O Research, thanks to a "different style of interconnect"—instead of going from the chip down to the motherboard and across to the other die, the chip is connected directly off the top of the package it's mounted on, and into the chip in the adjacent package with which it communicates. As a theoretical example, he envisioned a future processor needing to move a terabyte/sec of data between chips. Using today's interconnect and I/O would require "on the order of 150W" just for the I/O, he said; with this new interconnect scheme, that can be cut to just 11W.
Intel also discussed a prototype of a "universal" transceiver for system I/O (paper 20.7), with the ultimate goal to "potentially build a single I/O for many applications," noted Mooney. This technology adopts a scheme to adapt the transceiver to either system configuration or operating configuration to operate optimally, across a very wide range (5-25gbit/signal), and choosing the method of sending data between chips. Various options with this technology, including chip-chip, package-package, or board-board, copper, and even optical interconnects. — J.M.
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