Power management: key analog IC growth driver

04/01/2010

Executive OVERVIEW Power management is one of the hottest areas in semiconductors today. The ironic thing about the semiconductor industry (well-known to the analog guys) is this: the more the world goes 'digital', the more demand there is for analog ICs. That's because the real world is analog, so connecting the real world to the digital signal processors or microprocessors, which are at the heart of most electronic systems today, requires a variety of analog chips to condition and convert the signals between the analog and digital domains. At the heart of all this are power management chips. This article discusses the technical requirements for power management chips and trends going forward.

 Lou Hutter, Felicia James, Dongbu HiTek, Seoul, S. Korea

A major factor in the growth of power management ICs is the environmental push towards energy efficiency. Semiconductors, which have shown orders of magnitude higher energy efficiency reductions over the years, relative to other types of industries, have assumed a key position in this green movement. Moreover, semiconductors are ubiquitous in their applications, spanning across the three primary energy usage areas – transportation, residential/commercial, and industrial. Figure 1 shows the revenue breakout for 2009, estimated at $21.9B, and the 4-year CAGR, by market segment, respectively, using iSuppli estimates [1]. These values are well above the CAGR for the overall semiconductor market.

Figure 1. a) 2009F revenue % by end market. SOURCE: iSuppli; b) 2009-2013 CAGR by end market. SOURCE: iSuppli

Semiconductors are enablers to energy saving solutions. In particular, power management ICs refer to circuits that range from applications such as managing the power used within a larger electronic system such as a cell phone, TV or computer to applications enabling new power saving technologies including smart meters and grids or more efficient lighting solutions. In the first case, the power management circuitry is allowing the semiconductor application itself to be more efficient, while in the second case, the power management IC enables a broader diverse system (e.g., white goods, automotive, solid-state lighting, consumer products) to be more efficient [3]. This is clearly seen in the dramatic growth rate of power management chips for LED-backlit LCD TVs, as shown in Fig. 2 [2].

Figure 2. LCD TV and LED penetration vs. time. SOURCE: iSuppli

Technology implications

A key requirement of power management ICs is to deliver power, typically in the form of current, to a load device. To do this efficiently, the ICs must dissipate very little power on-chip. For the purposes of this discussion, an IC consists of three basic parts – the silicon, the metallization, and the package. To deliver good power management solutions, one must be good in all three areas. This section will discuss some of the key requirements for each.

Silicon technology requirements. Generally, power applications require high-current and high-voltage operation although usually not at the same time. Currents typically range from 200mA to 10A while voltages can range from 5V to 60V, with new applications – e.g., solar, solid-state lighting – pushing that limit to 100V, 700V, and beyond. These voltage levels are orders of magnitude above the 1.2V to 1.8V range of today's CMOS logic technologies, so clearly special technologies are needed to handle these applications.

The most typical technology used in today's power management applications is BCD (bipolar CMOS DMOS) [4]. This class of technology offers a wide range of components to the analog/power designer: bipolar transistors, low-voltage CMOS logic transistors, resistors, capacitors, diodes, high-voltage CMOS transistors. The typical power management chip has become quite sophisticated with on-board logic and analog control circuitry. Typical feature sizes for BCD technologies are in the 0.35 to 0.18μm range. Compare this to today's typical CMOS logic technologies that are in the range of 90 to 45nm. A key reason: BCD technologies are focused on higher-voltage applications, which dictate larger silicon design rules.

Figure 3. Cross-sectional view of an LDMOS transistor.

It is the DMOS, or double-diffused MOS, transistor that is the principal power component, acting as a high-current switch. There are several styles of DMOS transistors, but the most frequently used one is the LDMOS, or lateral DMOS, shown in Fig. 3, where the current flows laterally from the transistor source to drain region, under control of the gate electrode. The goal of this device is to be as close to a perfect switch as possible – i.e., zero resistance in the ON state, open circuit in the OFF state. Because size is money in this business, a key metric for an LDMOS transistor is its specific ON-resistance, R_sp, a measure of the resistance in a given amount of area. R_sp can be expressed as follows:

where R_ds(ON) is the drain-to-source ON-resistance (the resistance of the LDMOS device in its triode region), and Area is the size of the device. Units of R_sp are mΩ•mm². Plots of R_sp vs. BV are very useful yardsticks for power designers when evaluating the 'goodness' of a power technology with state-of-art R_sp values in the 12mΩ•mm² for a 20V LDMOS device [5]. Looking at equation (1), one realizes that for a given switch ON-resistance (R_ds(ON)), the smaller R_sp gives a smaller area which helps to explain the relentless pursuit of lower R_sp technologies through such means as lithography scaling, RESURF techniques, trench transistor approaches, etc. An equally important consideration for LDMOS transistors is their robustness, usually expressed as the SOA (safe operating area) [6].

Metallization requirements. Power management ICs must deliver their power to an off-chip load. Some form of metallization is needed to get that current from the silicon to the package. The best silicon-based LDMOS is of little value if the metallization connecting it to the outside world is insufficient.

Many of today's BCD technologies are based on CMOS logic processes, which have employed lithography scaling strategies over time. This scaling has reduced the metal thickness for patterning and planarization reasons. This reduction may be good for CMOS logic but is terrible for power devices. For technologies in the 0.35 to 0.18μm range, aluminum (Al) is typically used, while copper (Cu) is used for 130nm and below. Copper offers the illusion of lower resistance, due to its lower resistivity (1.7μΩ-cm vs. 2.8μΩ-cm for Al); however, the slotting rules needed to minimize CMP dishing often negate that advantage. Regardless, both films, Al or Cu, in their normal CMOS logic thicknesses offer disappointing options for power. As an example, consider the design of a 100mΩ switch (which would be needed to drive 1A with a maximum on-chip voltage drop of 0.1V). If one assumes that ~2 squares of metal resistance will be incurred to deliver the current off-chip (i.e., from the power device up to the bond wire), then the resistance budget is completely consumed by the typical 6000Å metal (Al), with nothing left for the silicon, bond wires, or package. The situation is only slightly better for Cu when density rules are applied.

The above analysis only considered the parasitic metal resistance between the power device and the bond pad. However, the effect of metal resistance can be even more insidious, as it creates IR drops within the power transistor itself, working to de-bias the device. In effect, if one applies a drain-to-source voltage (VDS) to the device terminals, the IR de-biasing in the metal lines causes the voltage across the true silicon drain-to-source region to be something less, thereby resulting in reduced current (since the LDMOS is just a resistor in the ON-state). Thus, to reach the required R_ds(ON) target, a larger sized LDMOS must be used. Effectively, this means that R_sp is not a constant, as desired, but actually increases as the size of the device (and the amount of metallization) grows.

Many BCD technologies now offer optional thick top metal layers, typically 3μm of Al. This cuts the parasitic metal resistance by a factor of 5, but at the expense of less-aggressive metallization design rules. Nonetheless, this is often a worthwhile trade-off.

Packaging requirements. Now that one has delivered the current efficiently to the bond pad, a good packaging strategy is needed to send it to the load. This packaging strategy must consider the bonding strategy and routing strategy used to get that current to the 'pins,' whether they are actual pins in a conventional package, or bumps in a flip-chip or chip-scale package (CSP).

Until recently, all bond wires were gold (Au). A typical 1 mil Au wire has ~50mΩ/mm resistance which is fine for logic, but not so fine for power. For example, a wire length of only 1mm is enough to consume half of the hypothetical resistance budget in the above example. Hence, multiple bond wires or thicker bond wires must be used on power devices. Due to cost and performance reasons, Cu wire bonding is now beginning to ramp into high-volume production.

Bond over active circuitry (BOAC) has become increasingly important for today's power management IC. In this technique, wire bonds are made directly over the power device rather than at the external bond pads. This eliminates much of the parasitic metallization routing resistance although it adds complexity to the packaging operation and device layout due to assembly-related design rules.

Other approaches attempt to remove the wire bonds, and their resistance, altogether. CSP is one of these methods; whereby the conventional package 'pins' are replaced by solder bumps, and the chip size effectively becomes the package size. Often the CSP 'pins' must be reconfigured for different end-user applications which is typically done by using a redistribution layer (RDL). This layer, done in the assembly site, typically consists of a thick Cu layer to connect the actual bond pads on the silicon die to the eventual bump sites for packaging with the thick Cu used to minimize the resistance adder. CSP production volumes are growing at extremely high CAGRs. One side effect of the movement toward CSP is the demand for thinner 'packages,' driving wafer back grind thicknesses to 200μm and below.

Other, more exotic, assembly and package techniques are being developed. While the silicon technology used to be the primary focus for power innovation, today, the packaging space is increasingly being explored for new opportunities to lower resistance and to minimize the temperature excursions from these high-power applications.

Power management trends

The demand for improvements and innovation in power management continues to drive interesting developments because of the increasing emphasis on power management and conservation through all types of applications. Additionally, the continuing expansion in mobile applications requires a small footprint, as well as long battery life.

Higher frequency applications. Today's switching regulators operate at frequencies in the range of 200kHz to a few MHz, but newer applications are pushing towards operating frequencies of 5MHz and above. These higher switching frequencies require smaller inductors and capacitors so the footprint and cost as well as energy of the resulting system decrease. As inductor size and capacitor size decrease, the option of integrating these components into the IC becomes feasible, which further simplifies the system bill of materials and complexity. However, the demand for smaller footprints (both horizontally and vertically) presents challenges in managing increased power density [7].

Digital power. Digital control of a power supply system is becoming more broadly accepted as a key means to manage the operating efficiency of a power system over all load conditions. Although a digital control system is more complex from an integrated circuit perspective — more CMOS gates, possibly more aggressive technology node, perhaps with embedded NVM — the efficiency advantages can be significant as a well-designed system can be constantly adapting and optimizing based on the load conditions. Whereas power management used to be considered an after-thought, today's low-power, portable systems benefit from the closed-loop controls this technique affords.

Energy harvesting solutions. Windmills and waterwheels come to mind as centuries' old examples of energy harvesting, and common examples today include wind turbines and solar panels. Another dynamic new field of energy harvesting revolves around micro-harvesting to drive hand-held applications. Simple examples of micro-harvesting are wrist watches that achieve power from the kinetic energy (vibration) supplied by the wearer or from solar energy. Sources for energy harvesting can include energy from vibration, temperature differentials, light, and RF waves [8]. Energy harvesting solutions frequently entail hybrid solutions that combine traditional energy sources with harvested energy and drive innovative power supply and management implementations. These implementations typically include energy storage, power conversion, and power management.

Conclusion

Power management is at the center of a tremendous amount of growth in the semiconductor industry, fueled by the explosion of portable power and consumer electronics, with growth rates well above the industry as a whole. However, the technical requirements are quite rigorous across silicon, metallization, and packaging. Finally, the increasing market demand has driven more focus and compelling new solutions.

References

1. M. Vukicevic, "Sophisticated Power Management Shapes Bright Digital TV Future," http://www.isuppli.com, 2009.

2. M. Vukicevic, "Power Semiconductor Orders Strengthen in Q3, Point to Stabilizing Conditions," http://www.isuppli.com, 2009.

3. BBC News, "Australia Pulls Plug on Old Bulbs," Feb, 2007, http://news.bbc.co.uk/2/hi/asia-pacific/6378161.stm.

4. D. Riccardi, et al., "BCD8 from 7V to 70V: a New 0.18μm Technology Platform to Address the Evolution of Applications towards Smart Power ICs with High Logic Contents," Proc. of the International Symp. on Power Semiconductor Devices, 2007, Jeju, Korea.

5. S. Pendharkar, et al., "7 to 30V State-of-Art Power Device Implementation in 0.25μm LBC7 BiCMOS-DMOS Process Technology," Proc. of the International Symp. on Power Semiconductor Devices, 2004, Kitakyushu, Japan.

6. P. Hower, et al., "Short and Long-Term Safe Operating Area Considerations in LDMOS Transistors," Proc. of the International Reliability Physics Symp., 2005, San Jose. USA.

7. Ali Ghahary, "Fully Integrated DC-DC Converters," Power Electronics Technology, Aug 2004. URL: http://powerelectronics.com/mag/power_fully_integrated_dcdc.

8. E. Torres, et al, "Electrostatic Energy-Harvesting and Battery-Charging CMOS System Prototype," IEEE Trans. on Circuits and Systems – I: Regular Papers, vol. 56, no. 9, September 2009.

Biographies:

Lou Hutter received his BS in math and physics from Northern Kentucky U. in 1976, and his MSEE from MIT in 1978 and is a senior vice president and general manager of the Analog Foundry Business Unit at Dongbu HiTek, 222-1, Dodang-Dong, Wonmi-Gu, Bucheon, Gyeonggi-Do, 420-712 Korea; ph.: +82-32-680-4140; email [email protected].

Felicia James received her BSEE from U. of Virginia in 1983 and her MBA from U. of Texas in 2000 and is the director of analog strategy at Dongbu HiTek, 1301 Central Expressway, Suite 125, Allen, TX 75013 USA; ph.: +1-214-509-6632; email [email protected].

More Solid State Technology Current Issue Articles
More Solid State Technology Archives Issue Articles