Allvia shows off its Si interposer data

02/01/2010

Nagesh Vodrahalli, VP of technology & manufacturing at Allvia, discussed some of the issues in developing through-silicon via (TSV) technologies with Solid State Technology/Advanced Packaging in conjunction with his presentation at the recent 3-D Architectures for Semiconductor Integration and Packaging conference (Dec. 9-11, Burlingame, CA).

 

Figure 1. Silicon TSV interposer. (Source: Allvia)

For front-side via processes, critical challenges include achieving void-free metal filling, high aspect ratio processing, stress in a Cu-filled via, and thin wafer handling post-TSV processing. Challenges for backside vias include isolation, backside contacts, high aspect-ratio processing, protection of the coated metal inside via, and thin wafer handling. Allvia, which has been working on many of these issues for over two years presented reliability data at the conference (see table). "We have solved most of the issues to the point where we can get a product qualification going," Vodrahalli told SST/AP. "We'll uncover additional issues as we scale up to run volumes, but most of the technical issues have been resolved." Allvia also provided to SST/AP its most recent data from its work on a silicon TSV interposer (Figure 1).

If the industry is to make the most of the advantages of using thinner wafers, however, the ability to handle them is a critical challenge. "Whether for frontside or backside via technologies, if you go to a thinner wafer, the processing cost of a silicon via becomes cheaper [...] except for the thin wafer handling portion," Vodrahalli told SST/AP. The basic processing such as etching the vias, metallization, and the fill becomes cheaper with a thinner wafer. "So there is a genuine need to go to thinner wafers," he noted, with potential performance gains including electrical and reduced package size.

Figure 2. Interposer on BT substrate. (Source: Allvia)

Today's thin wafer handling techniques have limitations of temperature, noted Vodrahalli—for example, the backside process temperatures for front-side vias will have to withstand solder reflow temperatures of about 260-270°C. "Unfortunately, most of the current wafer handling technologies peter out at around 200°C, regardless of what people claim," he said. "People claim 250-300°C, but it's still a problem to reach 250°C and beyond—they can't handle the higher temperatures needed for backend processing." Even at temperatures of around 250°C a lot of wafers will be lost, Vodrahalli said. When production goes to wafers at 250µm thick wafers and below, the industry will absolutely need a thin wafer handling technology that can withstand high temperatures and also withstand different chemicals. "Backside via technology without thin wafer handling technology is not going to be very real," he said.

Table GRC reliability data summary. (Source: Allvia)

Additionally, Vodrahalli pointed out, for backside vias, some of the passivation processes or the frontside protection processes need to withstand process temperatures higher than 300°C. "To get a solid isolation film, we would prefer to have a higher temperature capability for the handling than we can get with a standard TEOS process that can go up to about 350°C," he explained. "Today, the thin wafer handling process does not exist that can tolerate such a high temperature."

As a TSV foundry services company, Allvia is concerned with more than developing the required TSV process technologies; cost is also a factor. Vodrahalli noted that traditional bonding/debonding equipment is quite expensive compared to the usual equipment costs one would expect for backend processes. By working with equipment suppliers, the company is developing TSV solutions that have a cost model somewhere in between frontend and backend equipment and applications. The company is not, however, going into the equipment business, choosing to instead focus on process integration and recipes developed in conjunction with equipment suppliers. "The basic unit equipment exists, but the integration and sequence of operations is where we can have IP," Vodrahalli noted. — D.V.

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