IMAPS 2009: Fusion bonding for 3D/TSV, wafer-level/multichip packaging for MEMS

01/01/2010

Presentations at the International Symposium on Microelectronics (IMAPS, Nov. 1-5) included discussion of through-silicon via (TSV) /3D integration challenges and temporary bonding steps qualified for different process flows, and a wafer-level packaging (WLP) encapsulation process and stacked multi-chip package (MCP) for a MEMS variable capacitor and control IC chip.

EV Group's Thorsten Matthias presented his company's solutions for TSV/3D integration, with data showing that temporary bonding to a carrier wafer, thinning, backside processing, and subsequent debonding were qualified for several different process flows (session #WA5, paper #1).

Though Cu-Cu thermo-compression wafer bonding has shown promise for very high TSV density face-to-face integration applications, the researchers found that fusion bonding, with its cost-of-ownership advantages, is very attractive compared to metal-metal bonding. Among the other advantages of fusion bonding noted by Matthias: high alignment accuracy (because misalignment due to thermal expansion of the wafers is eliminated), high-throughput, and the ability to be inspected after pre-bonding prior to final annealing.

The main challenges of using fusion bonding, according to the researchers, are sensitivity to particles and surface roughness. An integrated cleaning module addresses the problem of particles, and the surface micro-roughness requirement of 0.5-2nm can be met with advanced CMP technology.

Alignment results with the EVG SmartView NT Aligner (400 alignments). (Source: EV Group)

The surface pre-processing step used by the group, called "LowTemp" plasma activation, modifies the wafer surface in such a way that the annealing temperature can be reduced to a range of 200-400°C. According to EV Group, such plasma activation enables the usage of fusion wafer bonding for 3D integration. Alignment accuracy for the group's research was verified using the EVG SmartView NT Aligner (see figure).

Also at IMAPS, Toshiba's Mitsuyoshi Endo reported on a wafer-level packaging encapsulation process and a stacked multi-chip package for an electrostatically actuated MEMS variable capacitor, and the control IC chip, respectively (session #TA5, paper #1).

Because a MEMS variable capacitor needs to be operated in a dry atmosphere (to avoid voltage shifts), and it is known that movable electrodes (in a MEMS capacitor) vibrate in a vacuum, the researchers needed a process that enabled the capacitor to be operated under atmospheric pressure. These were the motivating factors to develop a WLP encapsulation structure with hybrid thin-film (four thin-film layers) using standard backend-of-line LSI technologies. The first layer (SiO) is the cap layer; the second layer (polymer) is the plug layer; the third layer is the moisture barrier (SiN); and the fourth layer, formed in the polymer, protects the entire encapsulation from subsequent MCP processes.

The motivation for development of a stacked MCP for the control IC chip (that provides the actuation voltage to the MEMS capacitor) was to find a fabrication process compatible with the MEMS capacitor structure, because the control chip was to be integrated into the WLP package. Endo noted that although the fabrication process of the stacked MCP is based on a conventional packaging process, some of the processes had to be optimized to handle the fragile WLP encapsulation. The researchers, therefore, optimized a stacked MCP process, having also decided that chip-scale or system-on-chip (SoC) packages would be difficult to integrate with the MEMS chip.

Based on the reliability testing data (temperature cycling, accelerated moisture resistance, and moisture
eflow sensitivity), the researchers concluded that neither voids nor cracks were present in the MCP. Normal operation of the MEMS variable capacitor was confirmed up to 85% relative humidity. — D.V.

More Solid State Technology Current Issue Articles
More Solid State Technology Archives Issue Articles