Invensas demos DFD implementation of its xFD technology

11/01/2011

Invensas Corp., a wholly-owned subsidiary of Tessera Technologies, demonstrated the dual-face down (DFD) implementation of its new multi-die face-down (xFD) packaging technology at the Intel Developer's Forum (IDF, Sept. 13-15, San Francisco). The new technology targets the increased DRAM capacity and performance now needed by data centers; it's also aimed at notebook computers, tablets and smart phones that need better battery life with a reduced form-factor.

The wire bond-based packaging technology mounts ICs upside-down and staggers them in a "shingle-like" configuration, so the wire bonds poke through the bottom of the substrate, explained company president Simon McElrea. This gives an electrical advantage: "Because we remove spacers and face-up wire bonds, you get a super thin package that aids in heat transfer," he said. "And because you've staggered the die, you get heat transfer through the bottom chip as well as the top chip, without having to take all the heat through the die stack." The company says that heat transfer in the DFD package is improved 20%-30% in comparison to conventional dual-die packages.

The company reports that the new packaging decreases the overall component size with a 25%-35% savings in vertical height over conventional solutions, and enhances electrical performance with a 50%-70% improvement in speed-bin yield (see figure). "This is based on data from thousands of parts," McElrea told SST. Keeping both die with very short interconnects results in the equivalent of single-die performance, though there are multiple die in the package: "Instead of dumbing down the performance of the multi-chip package to your slowest chip, the top chip, you get the performance of the silicon itself," he said.

Sort yield advantage comparing DFD packaging vs. conventional DDP packaging. (Source: Invensas)

McElrea explained that xFD technology costs less to manufacture than conventional multi-die DRAM packages because it uses a parallel process flow???i.e., all the chips are stacked at the same time in one station, and then all the die are wire-bonded at the next station, so all of the pads are exposed in the stacking structure. Cost savings also comes from a significant reduction in gold and other material usage. Furthermore, the package is manufactured on existing wire bond assembly lines. ??? D.V.

Solid State Technology | Volume 54 | Issue 10 | November 2011

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