Integration and 3D-ICs driving developments in wafer bonding

10/01/2011

Thorsten Matthias, Eric Pabo, Viorel Dragoi, J??rgen Burggraf, Paul Lindner, EV Group, St. Florian am Inn, Austria

Megatrends driving wafer bonding are heterogeneous and 3D integration.

The first major boost for wafer bonding technology came from automotive safety devices. Capping of micro-machined cavities at the wafer level (thereby encapsulating a sensor in a controlled environment) enabled the surge of MEMS devices in the car, e.g., airbag sensors, anti-blocking devices or tire-pressure sensors. For safety devices, reliability and longevity are the most important requirements. Glass frit as a packaging material results in very large seal rings, which usually consume more real estate than the sensor itself, but the package is very reliable, and the bonding process tolerates a large range of incoming wafer parameters. Currently, many automotive MEMS devices are manufactured using glass frit wafer bonding.

Accelerometers and gyrometers were later adopted for consumer electronics applications, such as gaming devices and smart phones. Consumer electronics have a much shorter product life cycle, so nice-to-have gadgets have a different price structure than potentially life-saving devices. Reducing the package size was the main lever for lowering the cost of MEMS devices. Instead of glass frit, which creates seal rings with a width of up to 150??m, metal-based seal rings with a width of less than 10??m were implemented. For some devices, this reduction in packaging real estate resulted in 400% more dies on the wafer.

The current megatrends driving the technical evolution of wafer bonding are heterogeneous integration and 3D integration. Different functional entities of a device are manufactured separately and later integrated by wafer bonding. This enables a modular device architecture and thus a modular manufacturing supply chain. Device manufacturers can focus on their core competence, e.g., designing and building the ASIC, and then add standardized modules, such as logic controllers or memory, from other manufacturers. Stacking dies enables the electrical performance of a system-on-chip, but it reduces the design time, complexity and cost significantly. Integration of MEMS and CMOS was in fact a major driver behind the transition to 200mm MEMS manufacturing.

Modular integration

Implementing a modular integration concept requires standardization, not only for the device interface design, but also for process technology ??? specifically, the wafer bonding step. For many applications, the standardized bond interface is based on a planarized oxide layer and subsequent fusion bonding. In the past, spin-on-glass (SOG) was tried for creating planar bond interfaces, but today, chemical-mechanical polishing (CMP) is the preferred approach. Fusion bonding requires flat wafers with a surface roughness of less than 1nm, which is well within the capabilities of today's CMP equipment. Silicon dioxide (SiO2) is a known CMOS-compatible material, and oxide deposition and CMP can be performed on most wafers. The resulting bond interface does not imply any limitations to further downstream processing, i.e., further processing steps can happen in a high vacuum or at temperatures higher than the bonding temperature itself. Figure 1 shows the process steps toward a bond interface required for fusion wafer bonding.

Figure 1. Fusion wafer bonding enables a standard bond interface and standard integration scheme.

Fusion wafer bonding is a two-step process consisting of a room temperature pre-bond and an annealing step. Traditional annealing processes developed for SOI wafer manufacturing required an annealing temperature of 1100??C. A new surface treatment with plasma activation allows reducing the temperature to 200-400??C. This makes fusion wafer bonding compatible with fully-processed CMOS wafers. Figure 2 shows that high surface energy/bond strength is achieved with plasma activation, while a lower annealing temperature can be offset by extending annealing duration. This is very important for heterogeneous integration with different materials whose thermal expansion differs, e.g., gallium nitride (GaN)-on-Si or gallium arsenide (GaAs)-on-Si. Fusion wafer bonding for CMOS wafers is today the standard process for backside-illuminated image sensors on 200mm and 300mm wafers.

Figure 2. EVG's LowTemp plasma activation with nitrogen or oxygen plasma enables high bond strength at moderate annealing temperatures: a) nitrogen plasma, b) oxygen plasma.

3D integration was a major driver toward better alignment accuracy. Establishing electrical interconnects with through-silicon vias (TSVs) with a diameter as small as 1-2??m required alignment accuracies in the submicron range. The wafer-to-wafer alignment principle has to be in line with the goal of a standardized interface and integration scheme. Therefore, the traditional alignment principles based on backside alignment keys or infrared (IR)-transparent wafers are not flexible enough. One alternative is the EVG SmartView alignment technology, which uses alignment keys in the bond interface and does not rely on the wafers' IR transparency. Fusion wafer bonding can achieve excellent alignment accuracy as the pre-bonding step is occurring at room temperature. For high-temperature bonding processes, thermal expansion of the wafers makes it more challenging to maintain the alignment accuracy. At the IEEE 3D IC Conference in 2010, Soitec and IBM reported post-bond alignment accuracy of better than 250nm for oxide-oxide fusion bonding using the SmartView alignment [2], and SEMATECH reported sub-500nm post-bond alignment accuracy for copper-copper (Cu-Cu) thermocompression wafer bonding. The ITRS specifies a bonding overlay accuracy of 0.5-1.0??m for both global and intermediate interconnect levels for 2012-2015 [8]. The reported results show that wafer bonding is compatible with the required overlay accuracy. Figure 3 shows a cross-section of high density interconnects based on Cu-Cu thermocompression bonding.

Figure 3. Cross-section of Cu-Cu thermocompression bond interface; Courtesy of SiliconFile Technologies

After pre-bonding, the bond quality and the alignment accuracy of the wafer stack can be inspected, and if any defects are detected, the wafers can be separated and reworked. Inline metrology enables a direct feedback loop from metrology to wafer bonding. As fusion wafer bonding is very sensitive to particles, wafer cleaning and plasma activation have been integrated into modern bonding systems. This allows the highest possible repeatability of wafer surface conditioning.

The main attractiveness of fusion wafer bonding is that the annealing can be performed as a batch process. The cycle time for the bond process itself is only four minutes, whereas thermocompression bond processes typically have 30- to 60-minute cycle times. However, the oxide interface requires via-last integration schemes. For via-middle integration schemes, electrically conductive bond pads are required. Thermocompression Cu-Cu wafer bonding is performed at elevated temperatures of up to 400??C and by applying a force of up to 100kN. The bond mechanism is based on metal ion diffusion. Cu-Cu wafer bonding results in interconnects with the lowest possible electrical resistance as the two mating Cu surfaces form one solid metal structure. After the bond process, there is literally no bond interface visible and detectable any more [5]. However, the long cycle time of thermo-compression wafer bonding prevents widespread adoption. It would be very desirable to establish a Cu-Cu bond interface with short bond cycle times.

Cu-Cu bonds

Currently, there are multiple parallel development efforts taking place to shorten Cu-Cu bond cycle times. The first approach is to reduce the cycle time of Cu-Cu thermocompression bonding. During Cu-Cu bonding, the pure mechanical joint is established more rapidly than the high quality electrical interconnect. The trick is to keep the wafer stack just as long in the bond chamber until the mechanical joint is established and then perform the further annealing as a batch process. This concept goes back to initial development work at Rafael Reif's group at MIT [4] and has recently been re-examined for state-of-the-art metallizations by Young-Bae Park's group at Andong University [5].

The second approach is more radical as it targets room temperature bonding based on a hybrid oxide/Cu interface. The metal bond pads are embedded within an oxide film. The oxide-oxide bond interface allows spontaneous pre-bonding at room temperature and the electrical interconnects are established during the annealing step [6,7]. This spontaneous Cu-Cu fusion wafer bond can be performed in standard fusion wafer bonding equipment, such as the EVG Gemini FB. CEA Leti and Soitec demonstrated post-bond alignment accuracy of <200nm with SmartView alignment [7].

Heterogeneous integration and 3D-ICs have driven the technical evolution of wafer bonding. The basic goal is a standardized, modular design and manufacturing approach that reduces design, test and manufacturing costs. Because of the improvements in surface preparation, mainly CMP and plasma activation, fusion wafer bonding has become a standardized process for heterogeneous integration. Integrating cleaning and plasma activation into the wafer bonding enabled high-yield, high-volume production. Integrated metrology for bond quality and alignment accuracy allows a closed-loop feedback system. Requirements for high-density TSV applications have pushed achievable alignment accuracy to <500nm. Considering all these developments, wafer bonding has taken a big step towards standardized heterogeneous integration and 3D-ICs.

Acknowledgments

Gemini, SmartView are registered trademarks of EV Group.

References

1. IC Knowledge LLC news release, "FD-SOI determined to be more economical than planar bulk silicon CMOS processing," Georgetown, Mass., July 12, 2011.

2. G. Gaudin, et al., "Low temperature direct wafer to wafer bonding for 3D integration," Proc. IEEE 3D-IC Conf., M??nchen, 2010.

3. W. H. The, et al., "Post-bond sub-500nm alignment in 300mm integrated face-to-face wafer-to-wafer Cu-Cu thermocompression, Si-Si and oxide-oxide fusion bonding," Proc. IEEE 3D-IC Conf., M??nchen, 2010.

4. A. Fan, et al., "Copper wafer bonding," ECS Letters 2 (10) 534-536 (1999).

5. B. Kim, et al., "Effect of bonding process parameters on the interfacial properties of Cu-Cu direct bonds for TSV integration," Proc. IWLPC, San Jose, 2009.

6. www.ziptronix.com/techno/dbi.html

7. I. Radu, et al., "Recent developments of Cu-Cu non-thermocompression bonding for wafer-to-wafer 3D stacking," Proc. IEEE 3D-IC Conference, M??nchen, 2010.

8. International technology Roadmap for Semiconductors 2009 Edition, Interconnect, Tables INTC3 and INTC4, www.itrs.com

Thorsten Matthias is Director of Business Development at EV Group, Di Erich Thallner Strasse 1, 4782 St. Florian am Inn, Austria; ph.: +43 676 84531148; email [email protected]

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