AMAT's DRAM fab tools for denser transistors

09/01/2011

Applied Materials debuted three systems at SEMICON West for next-generation DRAM chip manufacturing: the Centura DPN HDTM system to improve the gate insulator scaling, the Endura HAR Cobalt PVD system for high-aspect-ratio (HAR) contact structures, and the Endura Versa XLR W PVD system for reduced gate stack resistance. (Also at SEMICON West, Applied decloaked a new Vantage Vulcan RTP tool for 2Xnm with backside wafer heating, and a new deposition and UV curing toolset for 22nm interconnects.)

Key transistor technologies, borrowed from logic devices, are helping DRAM chips achieve better performance and speed, overcoming a "memory wall:" the speed of the control circuitry that transfers data between the memory cell array and external data bus. These transistors are denser and more advanced, requiring new toolsets, Applied asserts.

Figure 1. The gate dielectric/oxide. Decoupled plasma nitridation enables high surface nitrogen content. (Source: Applied Materials)

The Applied Centura DPN HD system incorporates nitrogen atoms into the gate insulator to improve its electrical characteristics. The high-dose gate stack system for oxynitride gate scaling is said to increase DRAM periphery speeds, which enhance DRAM output. The HD technique builds on Applied's decoupled plasma nitridation (DPN) technology for advanced logic and memory fab. Decoupled plasma nitridation enables high surface nitrogen content (Fig. 1). Higher nitrogen content leads to higher capacitance, thus enabling equivalent oxide thickness (EOT) scaling, explained David Chu, global products management at Applied Materials.

Figure 2. Logic-derived expertise for fast DRAM implementation.(Source: AMAT)

The other members of the product trio addressing 2Xnm DRAM scaling challenges are the Endura HAR Cobalt PVD tool for periphery contacts, and the Endura Versa XLR W PVD tool for memory gate electrodes. Kevin Moraes, director of product management for metal deposition products, emphasized the impetus behind the HAR Cobalt PVD chamber (Fig. 2) and the need to transition from TiSi2 to cobalt. (Listen to the interview at electroiq.com/podcasts). Cobalt replaces titanium for transistor contact metallization on the Endura Cobalt system, depositing uniform films in high-aspect-ratio contact structures with 50% lower contact resistance than titanium. DRAM devices fabbed with the lower-resisitivity element can have faster switching speed and lower power consumption, he explained.

Figure 3. The Versa XLR W PVD chamber enables lower gate resistance required for 2Xnm. (Source: Applied Materials)

Meanwhile, the Applied Endura Versa XLR W PVD system is a tungsten-based tool that is said to offer a 20% reduction in gate stack resistivity (Fig. 3). The optimized reactor design improves consumable component lifetimes as well.

Together these two products (PVD Co) replace the much cheaper TiCl4 process, which has been used for many years but has shortcomings. An interesting sidenote to the introduction of these products is that using PVD instead of CVD runs counter to industry expectations. ??? D.V.

Solid State Technology | Volume 54 | Issue 8 | August/September 2011

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