Scatterometry measurement for gate ADI and AEI CD of 28nm metal gates

09/01/2011

Executive Overview For reduced gate leakage and enhanced device performance, many IC manufacturers utilize novel metal gate technologies instead of traditional poly silicon gates. The new materials and geometries required to form metal gates mean that new parameters control the optimization of device performance [1]. Traditional gate process control has relied heavily on scatterometry for ensuring that variation in structural dimensions remain in control, as some dimensional deviations can strongly affect device performance. A new-generation scatterometry tool with multiple extensions to traditional scatterometry technology is evaluated as a production process monitor for complex metal gate structures at the 28nm device node and beyond.

Y. H. Huang, C. H. Chen, K. Shen, H. H. Chen, C. C. Yu, J. H. Liao, United Microelectronics Corporation, Tainan Science Park, Tainan County 741, Taiwan, R.O.C. C. H. Lin, KLA-Tencor Corporation, One Technology Drive, Milpitas, CA, USA

Inline control and monitoring of the dimensions of the high-k metal gate (HKMG) structure are critical for device performance [2]. This paper focuses on dimensional measurement and control of a 28nm high-k metal gate for two layers: after-develop inspection (ADI) and after-etch inspection (AEI). For ADI, critical measurement parameters include side wall angle (SWA) and critical dimension (CD). The ADI structure is very challenging for traditional scatterometry measurements because the six different films under the photoresist (Fig. 1a) result in high correlation among measurement parameters. For the AEI process, nanometer-sized variations in the high-k and metal gate recess relative to poly Si width (Fig. 1b) affect device performance [3]. This recess represents another challenge for traditional scatterometry tools because nanometer-sized variations are difficult to detect. To qualify for production process control of these structures, the metrology tool must not only be sensitive to variations in all key structural parameters, but also be precise, non-destructive, and capable of production-worthy throughput. Critical dimension scanning electron microscopy (CD-SEM) nearly qualifies???except that not just CD but also shape metrology is required. Scatterometry emerges as the only near-term option.

Figure 1. a) ADI model and stack information; and b) AEI model and parametric description for HKMG.

We decided to evaluate a new-generation spectroscopic critical dimension (SCD) metrology tool, KLA-Tencor's SpectraShape 8810, to determine if it had the sensitivity and precision required for measurement of critical parameters on metal gate structures. The new tool's core technologies include a multi-azimuth ("multi-AZ") spectroscopic ellipsometer with broadband light extending into the deep UV portion of the spectrum [4] and a polarized, enhanced ultra-violet reflectometer (eUVR). The multi-AZ and multi-channel capabilities of this new tool promised enhanced critical parameter sensitivity and reduced correlation between parameters. We planned to gather data from process of record (POR), focus-exposure matrix (FEM) and design of experiment (DOE) wafers to characterize the performance of this new SCD tool on metal gate ADI and AEI structures. We also planned to compare metal gate AEI scatterometry measurement results to transmission electron microscopy (TEM) reference measurements. This evaluation process was designed to demonstrate the ability of this new-generation scatterometer to serve as a production process monitor for complex metal gate structures at the 28nm node and beyond.

Experiment and results

High-k metal gate ADI. The first study was designed to determine the sensitivity and precision of scatterometry measurement for a 28nm high-k metal gate ADI layer. Two wafers were used in the study. The first was exposed with a focus-exposure matrix (FEM), while the second was exposed with constant, standard (POR) lithography conditions. For the same DOE conditions, there were two targets in one field: one for an NMOS structure and a second for a PMOS structure. AcuShape2 advanced modeling software was used to break the parameter correlation. The floating parameters used in the model (the measurement parameters) include the critical parameters photoresist height (PR_HT), middle CD (MCD) and sidewall angle (SWA); plus the heights of BARC1, BARC2, hardmask and poly. The scatterometry measurement requirements included: 1) dynamic precision <0.1nm or <0.1degree; 2) sensitivity to dose and focus on the FEM wafer; and 3) baseline wafer verification.

Figure 2. MCD as function of focus and exposure for NMOS target (top) and PMOS target (bottom).

The MCD measured by scatterometry versus focus and energy exposure for both NMOS and PMOS targets are displayed in Fig. 2. The Bossung curves for the NMOS and PMOS structure indicate that scatterometry has good sensitivity to focus and exposure variations during photolithography.

Figure 3. Wafer maps of MCD and SWA for DOE wafer and baseline wafer.

The MCD and SWA of whole wafer map plots for the FEM wafer and the baseline wafer are shown in Fig. 3. The wafer maps show that MCD decreases from left to right for both NMOS and PMOS targets and the SWA is increasing from left to right. These results are consistent with the FEM DOE pattern. For the baseline wafer there is no clear pattern observed, as expected.

The dynamic precision of MCD, SWA and resist height (PR_HT) was measured on the baseline wafer: ten repetitions with wafer load and unload for 11 sites. The results showed that scatterometry has excellent precision with a demonstrated 3 sigma of less than 0.1nm for MCD and resist height, and less than 0.1 degree for SWA.

High-k metal gate AEI. To demonstrate the new tool's sensitivity and precision for the HKMG AEI profile, seven DOE wafers with varying process conditions were prepared. The DOE wafer varied three critical parameters, metal gate recess (MG_recess), high-k recess (HK_recess) and poly side wall angle (SWA), and two non-critical parameters, poly Si CD and hard mask (HM) height (Fig. 1b). The scatterometry measurement requirements for this HKMG AEI process layer were: 1) dynamic precision <0.1nm or <0.1 degree; 2) metal gate and high-k DOE sensitivity; and 3) correlation to the TEM reference measurement.

The high-k recess and metal gate recess are the most critical parameters in this application. Because the metal gate and high-k layer thickness under poly is very low, the sensitivity of the scatterometer to variations in the MG and HK recess is also very low. To improve the scatterometry measurement sensitivity and precision for the HK recess and MG recess, the multi-AZ and multi-channel approaches were used. 2D contour maps of MG recess and HK recess revealed that the variations in MG recess and HK recess across the wafer were within 1nm and followed a concentric pattern. The edge of the wafer had a higher MG recess and a lower HK recess.

HK recess and MG recess data from all DOE wafers showed that the SCD tool was able to recognize the MG recess and HK recess DOE splits. Poly BCD and SWA data were also collected for all wafers on the DOE list. The results showed that the new tool is able to distinguish poly BCD and poly SWA DOE splits.

The dynamic precision of critical parameters for HKMG AEI was measured on the POR wafer. As before, the 11-site measurement was performed ten times with wafer load and unload. The results showed that the tool has excellent precision for the critical parameters. The average of 3 sigma dynamic precision is less than 0.05nm for MG recess, 0.07nm for HK recess and less than 0.03 degree for SWA.

Figure 4. MG/HK CD and MG/HK recess correlation between SCD tool and TEM reference.

Metal gate AEI: correlation to TEM. To verify in-line scatterometry measurement accuracy, a transmission electron microscope (TEM) was used as a reference. The TEM measured two sites on each wafer, at the center and at the edge, for a total of 14 TEM data points in the DOE wafer set. The scatterometry measurement values were compared with the corresponding TEM values. The MG/HK CD and MG/HK recess results are shown in Fig. 4. The R² correlation of metal gate CD and high-k CD is about 0.97 and the slope is around 1.05. MG recess and HK recess are the most critical and challenging parameters. The SCD correlation with TEM shows an R² greater than 0.96 for MG recess and 0.95 for HK recess, and a slope around 1.0 +/- 0.03. For all critical parameters the R² correlation was greater than 0.95 and the slope was 1.0 +/- 0.05. These TEM correlation results confirm that the new generation SCD tool can be used as an in-line monitor for the 28nm high-k metal gate etch process in production.

Conclusion

As semiconductor structures become increasingly complex, they require ever more sophisticated metrology for characterization and process control. A new-generation SCD tool combines multi-AZ and multi-channel optical signals, providing the metrology performance required for advanced structures in metrics such as precision and accuracy. Data presented in this paper has demonstrated that this new tool has good sensitivity and measurement repeatability for the 28nm HKMG ADI process. For AEI, this tool has the sensitivity to track DOE conditions, and the measurement results correlate very well with the reference TEM measurements. With its high sensitivity, high throughput, and nondestructive measurement capabilities, the new scatterometry dimensional metrology system has proven to be suitable as a 28nm HKMG ADI and AEI process monitor.

Acknowledgments

The authors thank Xiafang (Michelle) Zhang, Russell Teo, Zhi-Qing (James) Xu, Sungchul Yoo, Chao-Yu (Harvey) Cheng and Jason Lin of KLA-Tencor Corporation for their contributions to this article. A more detailed version of this manuscript originally appeared in Metrology, Inspection, and Process Control for Microlithography XXV, ed. Christopher J. Raymond, Proc. of SPIE Vol. 7971, 79712O, 2011.

References

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2. M. Sendelbach, W. Natzle, C.N. Archie, B. Banke, D. Prager, D. Engelhard, J. Ferns, et al., "Feedforward of mask open measurements on an integrated scatterometer to improve gate linewidth control," in Metrology, Inspection, and Process Control for Microlithography XVIII, edited by Richard M. Silver, Proc. of SPIE Vol. 5375 (SPIE, Bellingham, WA 2004) pp. 686-702.

3. N. Collaert, M. Demand, I. Ferain, J. Lisoni, R. Singanamalla, P. Zimmerman, et al., "Tall triple-gate devices with TiN/HfO2 gate stack," 2005 Symp. VLSI Tech. Dig. of Papers, paper 7A-2.

4. T. G. Dziura, B. Bunday, C. Smith, M. M. Hussain, R. Harris, X. Zhang, J. M. Price, "Measurement of high-k and metal film thickness on FinFET sidewalls using scatterometry," Proc. SPIE Vol. 6922, (2008).

Contact author

Yu-Hao Huang is a senior engineer at United Microelectronics Corporation, Tainan Science Park, Tainan County 741, Taiwan, R.O.C.; ph.: 886-6-5054888 ext.11637; email [email protected]

Solid State Technology | Volume 54 | Issue 8 | August/September 2011

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