Intel hits 22nm stride with trigates

06/01/2011

Intel has taken the wraps off its next chip technology, a 22nm process utilizing a new 3D trigate architecture promising faster speeds and big power savings, which will ramp to volume manufacturing later this year. Performance and power improvements in the Moore's Law-extending technology are "like nothing we've seen before [...] far exceed[ing] what we typically see from one process generation to the next," observed Intel Senior Fellow Mark Bohr.

Chipmakers have been tinkering for years with post-planar CMOS technology and visions of trigate architectures surrounding the channel. Whereas traditional 2D planar transistors form a conducting channel in the silicon under the gate electrode when on, the trigate vertical structure replaces the flat 2D stream with 3D fins, conducting and controlling channels on three sides to provide "fully depleted" operation. (Note that Intel doesn't use SOI, another viable yet expensive pathway to achieving full-depletion.) Multiple fins can be connected together to increase total drive strength.

Compared with 32nm planar chips, Intel's new 22nm trigates deliver >50% power reduction at constant performance, or a 37% performance increase at low voltage. The 22nm trigate circuits (364Mbit array size) incorporate 3rd-generation HKMG and the same transistor/interconnect features as on 22nm CPUs, but only add 2%-3% to process costs (vs. 10% for FDSOI), Intel says. First processors incorporating the trigate structure process (P1270), code-named "Ivy Bridge," are targeted for production ramp in 2H11 (maintaining the 2-year "tock" cadence for new tech generations); a 14nm version (P1272) is slated for 2013, and a 10nm one (P1274) in 2015.

Analysts polled by SST generally had takes on Intel's 3D achievement addressing four themes:

Flexing manufacturing muscles. Intel has been tight-lipped about any manufacturing details and materials, but Bohr indicated the trigate structure adds about 2%-3% costs vs. the 32nm process, centered on etch/dep doping—still using immersion lithography and double patterning, but no new mask steps. Those higher wafer costs should be washed out by improved die density, though, points out Deutsche Bank analyst Ross Seymore.

Gartner analyst Dean Freeman noted the process demands tight control over litho issues, sidewall doping and roughness. Tom Halfhill, senior analyst with the Linley Group, further defines this into four areas: thicker layers of Si to etch the vertical fins, a more precise/challenging etch to create equal-dimension fins, a more difficult metal-gate step to deposit metallic material on all three sides of the fin, and more rigorous test/verification steps to ensure process control. Any variation in the fins or the metal-gate material thickness will affect transistor performance. (And the ability to vary the size of the fins on purpose supports circuit designs optimized for performance/clock speed, static leakage, or dynamic power, he noted.)

Chipworks' Dick James notes that the multigate structure "means a whole new set of design and layout paradigms," and that Intel won't be using a hybrid process (trigate SRAM, other areas planar).

Note that Intel isn't using SOI (as does GlobalFoundries, for example). SOI is another viable yet expensive pathway to achieving full-depletion; it adds 10% to process costs, vs. the 2%-3% for multigate, Intel claims. And also note that getting a trigate structure nailed down early "enables Intel to get the bugs worked out prior to implementing EUV," added Freeman.

Ahead of the curve, again. Intel says it's at least three years ahead of other chipmakers with the multigate implementation (no other chipmaker has announced 3D transistors). That translates to a process node generation (2 years) plus the chip giants typical lead at each node (1 year), says In-Stat analyst Jim McGregor. Freeman agrees that "they are at least a full year ahead at 22nm [and] probably a generation ahead at tri-gate transistors." Asserted Halfhill: "Nobody else will have these transistors at the 22nm node, and perhaps not even at the 14nm node," meaning it could be "at least four years before everyone else gets tri-gate transistors."

Intel had a similar headstart with its 2007 introduction of 45nm high-k/metal gate (HKMG) as well; the second-gen 32nm version came out in 2009. Only now are other chipmakers starting to ship HKMG, at the 32/28nm node.

A mobile play? Intel demo'd the 22nm trigate in a working group of systems (laptop, server, desktop) for a projected 2H11 release -- but the key may whether Intel can leverage the 22nm trigate transistors from its dominance in PC processors into a mobile market play. A parallel SoC process is being developed for Intel's Atom line of processors used in smartphones and tablets, which are just now being moved to the 32nm node.

"If Intel can move its lowest-power mobile processors onto its leading-edge manufacturing process in a more timely fashion, it would spell trouble for Intel's ARM-based competitors," notes Halfhill. McGregor agrees that Intel's smartest move would be to port Atom to the 22nm process, "even if it resulted in a short delay, likely a few months." Ramping new processes as quickly as possible, and on the highest-volume products (for Intel it's PC processors) is the best way to reduce costs, maximize ROI on process R&D, and gain competitive advantage. But for increasingly important and lucrative non-PC consumer electronics—e.g. handsets, where a billion of units are sold—"Intel needs to leapfrog the competition if it hopes to unseat the incumbent semiconductor suppliers," he notes. "While moving the upcoming Atom products to 22nm would still not guarantee Intel success in the consumer electronics markets, it could provide a must needed boost."

Glen Yeung of Citigroup agrees, saying the multigate move "will vault Intel squarely into the battle for mobile devices." Thermal design points for handset/tablet processors could drop to 0.5W-1W—"all else being equal, clearly competitive with ARM," with double the notebook battery life.

Intel as a foundry? With its process technology headstart, Intel could, if it wanted, use the new 22nm trigate structure to open up more business as a foundry (it's already reportedly working with two fabless partners). The company's process technology toolkit is without peer: low-power, low-leakage, fully depleted transistors, which are attractive features to companies designing for consumer portable devices. "With rare exceptions, such as Samsung, ARM licensees rely on independent foundries for their chip manufacturing—and the foundries are years behind Intel in tri-gate transistors," notes Halfhill. Gleacher & Co. analyst Doug Freedman agrees: "We believe foundries are working on similar technology but remain 18-24 months behind Intel's ability to bring the technology to market (expect attempts at 14nm)." — J.M.

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