IITC: BEOL beyond 22nm, CMOS-compatible CNTs

06/01/2011

SST caught up with two presenters from this year's IITC conference in Dresden to get more details about their interconnect technology research. (These and more IITC podcast interviews are available at electroiq.com/podcasts.html.)

Shyng-Tsong Chen, lead integrator for back-end integration at IBM (Albany Nanotechnology Center), offered an in-depth summary of the work in Cu dual-damascene interconnects ("64nm pitch Cu dual-damascene interconnects using pitch-split double-exposure patterning scheme"), and their extendibility to 56nm-pitch interconnects. The technology will be needed for back end of line (BEOL) interconnects beyond 22nm devices.

Figure 1. Via chain SEM cross-section along M1 line direction (upper) and along M2 line direction (lower).

The research was motivated by enabling sub-80nm-pitch patterning. The group used a self-aligned via (SAV) lithography
eactive ion etch (RIE) scheme to create vias confined by line trenches. According to the paper, an undercut-free post-RIE trench profile enabled good metal fill. Figure 1 shows post-chemical-mechanical planarization (CMP) cross-section scanning electron microscopy (SEM) images along the M1 line and M2 line directions. As noted in the paper, the upper image shows that the V1 via size is defined by the M2 line above as a result of the SAV process. The lower image shows the V1 via tapered along the M2 line direction.

Figure 2. Single CNT contact hole resistance as a function of the contact height for CNT coated with SiO2 (solid line) and Al2O3/SiO2 (dotted line).

Highlighting work in carbon nanotubes ("Electrical characterization of 150nm CNT contacts with Cu damascene top contact") Marleen van der Veen, senior research scientist at imec, explained the process technologies and steps used to grow the CNTs and the properties and attributes of the multi-walled CNTs (MWCNT) that resulted (Figure 2). As noted in the paper, the lower slope for the Al2O3 pre-coated CNT implies a three times better CNT resistivity than the SiO2-coated ones.

Figure 3. SEM images from different stages of the integration in 150nm contact holes a) before damascene litho and b) after barrier deposition and Cu fill.

The researchers took the integration process for 300mm contacts and transferred it to 150nm contact holes compatible with the module for 130nm device technologies (Figure 3). The researchers maintain that because CNTs grown from different recipes and processed under different conditions can be rapidly benchmarked, they believe that their work will be important for manufacturing CMOS-compatible CNT interconnects, as well as for improving CNT interconnect resistance in advanced CMOS interconnects. — D.V.

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