3D IC toolset readiness, Cu bonding, interposer failings

05/01/2011

The recent IMAPS Global Business Council Meeting and Device Packaging Conference (mid-March in Ft. McDowell, AZ) was the source of some significant new developments in the areas of 3D IC and fan-out wafer-level packaging.

Matt Nowak, senior director at Qualcomm, reviewed the key attributes of 3D ICs, including performance enhancement, improved power efficiency, formfactor miniaturization, and cost reduction. From there, a question arises—can 3D ICs can take the place of scaling as CMOS technology appears to slow (or stall)? He concludes:

• Yes—if performance enhancement and power reduction are the primary motivation.

• Yes—if form factor miniaturization is the only motivation.

• No—if cost reduction is the primary motivation. (3D with TSVs can provide cost reduction benefits, if cost improvements derived from CMOS scaling diminish in future nodes, e.g. due to advanced lithography and FEOL costs.)

Sitaram Arkalgud, director of SEMATECH's 3D IC program, shared the organization's perspective on the readiness of 3D IC toolsets (see figure below).

Taiji Sakai of Fujitsu indicated that the demand for tighter-pitch bonding has moved the industry to copper pillar bumping but that the time/temp bonding requirements of direct Cu-Cu bonding is keeping companies from moving to that technology despite its electrical performance advantages. He revealed that if the Cu bumps are planarized by cutting with a diamond bit vs. the normal CMP process, a "amorphous-like layer" is produced at the surface which allows Cu-Cu direct bonding at 200-250°C (30min) vs. the >350°C (30min) required for a CMP'ed surface.

Paul Siblerud of Applied Materials announced that EMCD 3D consortium, having met its goal of $150/wafer, will be ending this summer.

Rumors going around at this year's IMAPS-DPC were concerned with interposers reportedly failing in thermal cycling (TC) reliability tests. Reportedly, when the interposers are populated with unequal size or thickness silicon chips or chip stacks, the stresses generated on the interposers during TC causes the interposers to break. Ron Huemoeller, VP of 3D packaging for Amkor, confirmed that this indeed was an issue, but that Amkor had been able to engineer around it. He also revealed that the underfill process for the Xilinx program took more than a year get to a reliable, manufacturable state.

At GBC, Suresh Ramalingam of Xilinx discussed their stacked silicon interconnect technology (SSIT). The 28nm Virtex-7 SSIT will reportedly use TSMC fabricated 100µm thick silicon interposers with 10-12µm Cu TSV and 65nm interconnect. The micro-bumps are Cu-SnAg alloys at 45µm pitch.

Amkor's Huemoeller also offered a roadmap for memory stack usage (see figure).

During an excellent DPC panel session on fan-out packaging, Navjot Chhabra, director of advanced packaging for the Freescale RCP fan-out program, indicated that they are in qualifications with "industrial and automotive products."

Tom Strothman, director of business development for STATS ChipPAC, indicated that eWLB is today less costly than FcBGA. While STATS is currently running a 300mm line for production of eWLB, John Hunt, director of engineering for ASE, commented that "demand just does not warrant putting 300mm capacity in place." It was revealed that Infineon is the only commercial customer for eWLB today, with STMicroelectronics being very close.

While all of the eWLB licensees are proposing fan-out packaging on panels, Hunt commented that ASE was "the only company who has tried to do this [...] I can tell you that if we move forward with this approach it will require a totally new materials set." He indicated that they are attempting this work on 1/4 panels, not full PWB panels, and that obviously they cannot use molded underfill (MUF) to encapsulate the large substrates. — Dr. Phil Garrou contributing editor

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