High-k etch performance for next-generation logic gate stacks
12/01/2008
R. Wise, W. Yan, Y. Zhang, IBM Microelectronics
N. Gani, N. Sun, M. Shen, T. Lill, Applied Materials
Dry etching is essential for high-performance metal gate/high-k devices at 45nm and beyond. Unlike SiO2-based gate oxide that can be readily etched in HF solution, wet etching of high-k results in erosion of the nitride cap layer and undesirable high-k profile undercut at the gate. This paper presents the key requirements for etching high-k gate dielectrics in logic gate applications, and explores dry etching options to meet these requirements. The effects of substrate temperature (ambient to >200°C) are investigated in detail.
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Conventional Moore’s law scaling is no longer adequate to meet transistor speed requirements for the 45nm technology node and beyond. In conjunction with continued transistor gate length scaling, conventional polysilicon gates are being replaced by metal gates, which overcome the polysilicon depletion effect that adds up to 0.5nm to the effective gate oxide thickness. TiN, TaN, TaSiN, TaC, WN, and W are some of the metals being investigated for these applications. In addition, to address gate leakage by electron tunneling through progressively thinner conventional SiO2-based gate oxides, high-k gate oxide based on HfOx will be integrated into the filmstack, presenting a new challenge in the device manufacturing process flow.
Gate stack engineering
In the conventional gate-first scheme, the high-k film from the source-drain areas must be etched first. Key requirements for this step are: 1) vertical high-k profiles with the ability to control the profile from taper to undercut for a large process window; 2) zero source/drain silicon recess, especially for fully depleted SOI devices where the top silicon thickness is on the order of 10nm; 3) residue-free open areas; and 4) at least 10:1 selectivity to the nitride mask.
In previous high-k etch studies, both wet and dry etching techniques were investigated. Wet etch relies on creating a damaged high-k layer with an inert plasma (e.g., argon) followed by subsequent removal of the high-k layer in a sulfuric/phosphoric acid mixture [1]. However, it suffers distinct drawbacks: 1) uncontrolled undercut of the high-k layer and 2) poor selectivity of the wet-etch-to-nitride film. Excellent nitride selectivity is critical as nitride is used as a cap layer for the poly gates; excessive loss of this mask results in undesired SiGe epitaxial growth on top of the poly gates during the SiGe embedding process.
Dry etching of metal oxides and high-k films has been extensively studied. Sha and Chang studied plasma etching of ZrO2 and HfO2 in BCl3/Cl2 plasmas as a function of ion energy, pressure, power, and gas composition, and have proposed a phenomenological model that describes the etch rate as a function of these parameters [2]. Kota et al. investigated low temperature (60°C) HfOx etching based on BCl3 chemistry and have shown that it is possible to achieve vertical high-k etch profiles without source-drain silicon recess [3].
To date, few studies have addressed the effect of low vs. high substrate temperature (65°C to >200°C) on high-k etch characteristics. Helot et al. studied HfO2 etching with Cl2/CO etch chemistry between 152°C and 352°C, showing that the formation of a chlorine-rich carbon layer suppresses the SiO2 etch rate, which enables HfO2/SiO2 selectivity of 15:1 [3]. Others show that low temperatures (40°C-70°C) are adequate for etching high-k with excellent selectivity to Si/SiO2, but have not investigated the process margin of a room-temperature etch process in terms of high-k foot control, residue control, and HfO2/SiO2 selectivity [4,5]. Here, we present a systematic study of substrate temperature effects on high-k (HfOx) etch characteristics.
Experiments
Experiments were conducted in a plasma-etch reactor, with inductively coupled source and bias powers (both 13.56MHz). The dual-coil source design enables control of plasma density uniformity across the wafer by varying the current ratio between the inner and outer coils [6]. Neutral species density uniformity across the wafer is controlled by a tunable gas nozzle that distributes gas flow between the reactor’s center (convective flow) and edge (diffusive flow) [7]. The wafer sits on a high-temperature ceramic electrostatic chuck that operates between 130°C and 220°C. Thermal conductivity between the chuck and the wafer is established by cooling the back side of the wafer with helium. Experiments performed at lower cathode temperatures were carried out in a similar reactor with a dual zone, actively heated coulombic chuck that operates in the 10°C-90°C range.
The HfOx film etched in the experiments constituted the gate oxide for a 45/32nm metal gate/high-k gate stack consisting of 193nm PR/BARC/TEOS (hard mask)/ poly silicon/ TiN/HfOx/SiO2/silicon substrate. The hard mask/poly/TiN was etched using PR mask followed by an in-situ PR strip. Etching high-k requires clearing approximately 2-5nm of HfOx film using a TEOS (or nitride) mask and stopping on the 0.5-2nm SiO2 layer.
Both Cl2 and BCl3/Ar etch chemistries were studied. At high temperature, the etch process is predominantly chemical. No intentional bias power is used; ion energy is defined by the DC self-bias that the cathode develops as a result of higher plasma potential. Several BCl3/Ar ratios were used, source power was varied by a factor of 3, and pressure by a factor of 5.
BCl3-based etching of HfOx at room temperature has been thoroughly characterized in a number of studies. Olivier et al. examined the composition of etch byproducts that result in high HfOx/SiO2 selectivity [5]. Wang and Donnelly investigated the effectiveness of a dilute H2 plasma for removing boron residue from a HfOx surface etched by BCl3 chemistry [8].
Etch rate and selectivity
Figures 1 and 2 show the Arrhenius plots for the HfOx etch rate as a function of temperature for Cl2 and BCl3 chemistries, respectively. For Cl2 etching, the temperature dependence suggests an activation energy of 7.1kcal/mol. The HfOx etch rate ceases to increase linearly with temperature at very high temperatures (>250°C), because etching becomes reactant-adsorption limited.
 Figure 1. Effect of temperature on HfOx etch rate with Cl2 chemistry. |
In contrast, BCl3 etching shows a significantly lower activation energy (3.6kcal/mol), suggesting that it is easier to etch HfOx with BCl3 than with Cl2. This may be the result of boron acting as a reducing agent that facilitates oxygen removal from HfOx by forming BxOyClz compounds (B2OCl4, BO2Cl5, and (BOCl)3 [2]. In addition, the overall activation energy with either chemistry is much less than the heat of sublimation of HfCl4 (23.8kcal/mol [9]), suggesting that ion-assisted etching is lowering the energy barrier.
 Figure 2. Effect of temperature on HfOx etch rate with BCl3 chemistry. |
The choice between Cl2 and BCl3 as the main etchant is made based on the HfOx/SiO2 selectivity. Figure 3 shows the HfOx etch rate with BCl3 chemistry as a function of temperature at different source powers. In general, the etch rate increases with increasing source power. At low temperature and source power the etch rates are too low (2-3nm/min) and are impractical from a production point of view. Increasing source power to 3x at low temperature (80°C), however, shuts down the HfOx etch. But at high temperature (e.g., 220°C), etch rates >10nm/min can be obtained.
 Figure 3. HfOx etch rate as a function of temperature at different source powers with BCl3 chemistry. |
Figure 4 illustrates SiO2 etch rate, and hence HfOx/SiO2 selectivity, as a function of temperature. The SiO2 etch operates in a shutdown regime over most of the parameter space investigated, except at higher temperature and low source power, where a finite SiO2 etch rate is seen. Thus, it is easy to obtain infinite HfOx/SiO2 selectivity with BCl3 chemistry almost independent of wafer temperature, but the HfO2 etch rate at low temperatures is too slow for practical application. Joubert et al. have explained the high selectivity obtained with BCl3 chemistry as the result of preferential BCl-based polymer formation on the surface of the SiO2 [5]. Under conditions shown in Fig. 4, SiNi etch was also found to be in deposition mode; hence, it is expected to be a suitable hard mask for the gate stack.
 Figure 4. SiO2 etch rate as a function of temperature at different source powers with BCl3 chemistry. |
Compared with BCl3 chemistry, Cl2 is impractical as a main etchant as its HfOx/SiO2 selectivity is very low; even with CO/O2 added to the chemistry, selectivity increases only to 15-20:1 [4]. The low HfOx etch rate at low temperature (80oC) observed above can be increased by adding bias power to sputter the BCl-based polymer from the surface (Fig. 5). However, while this significantly increases the HfOx etch rate, the SiO2 etch rate rises much faster, thus reducing selectivity to less than 2:1. Nevertheless, with low source and 10W bias, an HfOx etch rate of approximately 8nm/min is obtainable with infinite selectivity to SiO2. Joubert et al. found a similarly narrow window for etching HfOx at room temperature (<10W bias) and were able to enlarge it by diluting the etchant with argon [5]. In the present study, the baseline process was already heavily diluted.
 Figure 5. Effect of adding bias power to HfOx and SiO2 etching with BCl3 at low temperature (80°C). |
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HfO2 profile and residue control
Adding 10W bias power at 80°C modifies etch from chemical to physical. Figure 6a shows that the added bias power combined with low-etch byproduct volatility has produced a 3-4nm high-k foot on both ISO and dense profiles. With zero bias and a wafer temperature of 150°C, however, greater byproduct volatility promotes a more chemical etch, reducing the foot to 2-3nm (Fig. 6b). Further increasing the wafer temperature to >200°C enhances the chemical etch action yet again, producing a foot-free (<1nm) high-k etch profile (Fig. 6c).
 Figure 6. High-temperature etching minimizes the foot at the high-k/ SiO2 interface. |
Kota et al. have published high-k etch profiles with no foot and zero silicon recess for poly gates on high-k (no metal gate layer) obtained at low temperature [3]. But details of the etch process were not published and, based on the findings of the present study, the process window to obtain such results is likely to be too narrow for practical use. Moreover, further narrowing of the process window is anticipated, as achieving the appropriate work function for the metal will likely necessitate additional thin layers of other exotic materials between the metal gate and high-k layers.
Figure 6 TEMs illustrate two additional features. First, regardless of the wafer temperature during etching, silicon recess in the source/drain regions is almost zero, owing to the infinite HfOx/SiO2 selectivity possible with BCl3 chemistry. It should be noted that at low temperature, a tradeoff exists between high-k profile control and source/drain recess. Although one way to remove the high-k foot at low temperature would be to increase bias power, this would result in source/drain silicon recess, because HfOx/SiO2 selectivity will no longer be infinite. This tradeoff does not exist at >200°C, where both a vertical high-k profile and zero recess can be achieved simultaneously. Second, some of the TEMs show a bird-beak under the high-k (still with zero recess), especially as the high-k foot gets smaller. This bird-beak appears after the TiN etch (stopping on HfOx), and is not an artifact of the high-k etch itself.
 Figure 7. High-temperature etching eliminates high-k etch residue ??? examples at a) 80°C, b) 150°C, and c) 220°C. |
Etch residue in the open area was also studied for the various process conditions used. Figure 7 shows that residue was present in the open area on HfOx etched at 80°C and 150°C, but was absent at temperatures >200°C. We are currently analyzing the material composition, but speculate that the residues are redeposited etch byproducts that exhibit low volatility at low temperature. Adding a small amount of bias power at low temperature could completely eliminate this residue, but would compromise the source/drain silicon recess. At >200°C, though, the wafer is hot enough to promote byproduct volatility and eliminate the residue without the need for bias power.
For the high-temperature condition, the etched HfOx surface was also analyzed by TXRF for traces of Hf residue. The post-etch/pre-clean concentration of Hf was measured as 1.5E11 atoms/cm2 decreasing to <1E10 atoms/cm2 after wet clean.
 Figure 8. Optimized HfOx etch performance at >200°C with BCl3 chemical etch shows a) good profile, b) zero silicon recess, and c) residue-free surfaces. |
Figure 8 illustrates results of the optimized high-temperature (220°C), zero bias high-k etch process using BCl3 chemistry. Vertical HfOx profiles were obtained with zero source/drain silicon recess and residue-free surfaces.
Conclusion
high-k gate dielectrics will be integrated into transistors for logic devices at the 45nm technology node and beyond. high-k profile undercut and poor selectivity to the nitride hard mask limit extendibility of conventional wet or dry/wet etching schemes for these high-k gate dielectrics. However, high-temperature dry etch promotes etch byproduct volatility and chemical etching, thereby opening up the process window to make possible vertical high-k profiles with zero silicon recess and residue-free surfaces.
The authors would like to acknowledge the contribution to this article of Shashank Deshmukh, who received his Ph.D. in Chemical Engineering from the University of Houston.
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Rich Wise received his PhD in chemical engineering from the U. of Houston and is senior technical staff member at IBM Microelectronics, 2070 Rte 52, Hopewell Junction, NY, USA; Ph.: 845.892.9077; email [email protected].
Wendy Yan received her PhD in ceramic science and engineering from Rutgers U. and is senior development engineer at IBM Microelectronics, 2070 Rte 52, Hopewell Junction, NY, USA. Phone 845.892.9043; email [email protected].
Ying Zhang received his PhD in physics from the State U. of New York at Albany and is research staff member at IBM Research, TJ Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY 10598-0218 USA; ph.: 914.945.2238; email [email protected].
Nicolas Gani received his BSc in chemical engineering at the U. of California, Berkeley and is process technology manager at Applied Materials, Inc. 974 E. Arques Ave, Sunnyvale, CA 94085 USA; ph.: 408-584-1318; email [email protected].
Noel Sun received his BSc in chemical engineering at the U. of California, Berkeley and is senior process engineer at Applied Materials, Inc.
Meihua Shen received her PhD in chemistry at the U. of Rochester, NY and is senior director, process technology at Applied Materials, Inc.
Thorsten Lill received his PhD in physics at Albert Ludwigs U., Freiburg, Germany and is VP applications and technology development at Applied Materials, Inc.