Using combinatorial science to qualify new processes and materials
12/01/2008
J. Hillman, ATMI, Inc., Danbury, Connecticut, USA
The introduction of new materials into semiconductor manufacturing process flows is generating unprecedented improvements in integrated circuit (IC) performance. At the same time, the associated risks and costs are increasing exponentially. For semiconductor performance trends to continue, it will be critical to identify suitable combinations of new materials and integration approaches while containing development time and cost. This article presents results of applying combinatorial science to thin-film stacks early in the development cycle.
Combinatorial science entails highly automated testing in which many different types of compounds (or multiple variations of materials) are evaluated simultaneously under controlled conditions. Originally adopted as a means of reducing development time and cost in pharmaceutical research, combinatorial techniques are now being applied under a variety of circumstances in semiconductor manufacturing.
High productivity development (HPD) is a methodology in which ATMI applies combinatorial science directly to thin-film stacks and device structures to resolve critical materials and process needs. This approach provides information on process integration and device performance early in the development cycle. Additionally, new methodology tools allow the initial stages of this work to take place in the development laboratory, minimizing development costs.
As VLSI Research projects R&D costs to rise to more than $100B in 2010 from $45B in 2006, managing materials development costs is vital to industry profitability [1]. A combinatorial methodology can screen out many false leads, highlight promising avenues, and correlate device performance with analytical results early in the development process. The result is faster identification of robust solutions, reduced time-to-market, and lower development costs relative to conventional approaches.
Creating faster learning cycles
New materials development processes typically follow discrete stages: materials R&D, unit process R&D, process integration, and device performance optimization. These stages are further separated by the fact that materials suppliers focus on materials R&D at the front end of the development cycle, while equipment manufacturers focus on unit process development, and device manufacturers focus on integration and device performance optimization. Information flow between these three disciplines is limited and movement from one phase to the next is gaited by the testing or qualification results of prior steps.
Rather than organized sequentially, HDP tasks are separated into roughly concurrent primary, secondary, and tertiary screening phases. Primary screening utilizes coupons of relatively inexpensive blanket substrates. A 300mm wafer can be separated into six individual coupons. Up to 32 site-isolated formulation experiments can be performed simultaneously on a single coupon (or 192 independent experiments per 300mm wafer). This capacity to process massively parallel experiments enables rapid ranking of a large number of candidate formulations. Then, only the candidate formulations that best meet the screening criteria are carried forward to secondary screening.
In tertiary screening, the number of candidate formulations has been narrowed significantly. Thus it becomes practical at this stage to utilize more complex, patterned wafers for development experiments. The purpose of tertiary screening is to integrate the optimized processes that resulted from secondary screening with upstream and downstream processes to fabricate relevant electrical test structures. The output of the tertiary screening step includes device performance data that builds on the learning from primary and secondary screening.
The ability to process many site-isolated experiments in parallel, coupled with rapid feed back and feed forward of experimental data, results in significantly shorter learning cycles. Many experiments are conducted simultaneously, across multiple materials, under conditions that are relevant to real production environments. While the use of fewer wafers and chemicals also reduces expense, the biggest gain is the yield in useful data.
Accelerating process development
As we couple this combinatorial approach with expertise in materials science and interface engineering for end users, we see that many potential process and materials solutions can be intelligently screened in a fraction of the time that would be required for conventional development. At the same time, the method yields a rich data set that includes statistically optimized process windows and parametric device performance data. All of this can yield the best possible solution more quickly than ever before.
Several materials companies utilize combinatorial methods for formulation discovery. HPD applies these techniques at the wafer level, providing improvement not only in formulation discovery, but also in process development, integration, and device performance optimization.
These improvements can be illustrated in the application of combinatorial methods to optimize a copper post-CMP cleaning process aimed at improving copper surface roughness. Recently, a major Asian foundry was faced with the need to improve copper surface roughness as it transitioned to the 45nm technology node. First, combinatorial screening was utilized to develop an optimized post-CMP cleaning formulation. This work was done using copper line structures that had been polished in the fab, but not yet cleaned. The post-CMP cleaning process was tuned to maximize cleaning efficiency, and to minimize both the copper surface roughness and the copper line resistance.
The optimized process was then integrated with down-stream processes to create device structures to test the effects of the optimized post-CMP cleaning process on parametric and reliability based wafer-level electrical performance. This data set assured the company that risks inherent to scale-up had been minimized, and lowered the barrier to getting the new formulation qualified for high-volume manufacturing.
 Figure 1. Roughness of a copper post-CMP clean improved from a) 6nm rms to b) 1nm rms employing 1320 experiments and 3630 characterization sets in 3.5 weeks. |
As shown in Fig. 1, copper surface roughness was improved significantly. AFM measurements quantified the improvement from 6nm rms to 1nm rms. The improvement in surface roughness was shown to have a direct and positive impact on the copper line resistance. In all, 1,320 experiments were conducted in 3.5 weeks using just 16 wafers and <$100 worth of chemicals. Had the same optimization been conducted using conventional methods, experimentation is estimated to have required in excess of six months; wafer and chemical costs would have been substantially higher. Moreover, conventional methods would have required the device manufacturer to take HVM equipment out of production to complete the optimizations. Instead, the combinatorial lab work allowed offline optimization of formulation, process, and device performance.
Leveraging high-volume data collection
High throughput experimental capability must be matched by an equally high-volume analytical capability. Combinatorial methods generate a wealth of data very quickly, so experimentation must be managed by state-of-the-art informatics systems. Informatics software supports the design and execution of statistically relevant tests, and then monitors, records, and organizes the experimental results. These data not only inform current assessments, but also serve as a resource that may be accessed to inform later experimental design and address subsequent problems.
One such example centers on a process optimization challenge faced by another Asian foundry. The company found its process of record plagued by copper oxide island formation. The culprit was thought to have been the copper CMP slurry. Electrochemical analysis proved to be a rapid method for measuring copper surface oxidation, and combinatorial screening of three slurries quickly eliminated slurries as a source of the problem. Data generated in prior post-CMP cleaning development work had indicated that the post-CMP cleaning formulation played a significant role in maintaining copper surface stability. These data were then used to guide evaluations of six post-CMP cleaning formulations.
 Figure 2. Effort to stabilize copper surface and eliminate CuOx island formation reveals post-CMP clean is the key factor in stabilizing the copper surface. |
The subsequent experimental and analytical work traced the root cause for copper oxide island formation to poor copper surface stability resulting from the post-CMP clean. Generally, higher pH formulations were shown to leave a more stable copper surface. In particular, a high pH formulation with a novel corrosion inhibitor was shown to eliminate the copper oxide island formation problem and also dramatically extend the post-CMP queue time. Figure 2 shows the results of the post-CMP clean optimization work.
Speeding device qualification
In conventional development, materials specifications are set to drive device performance. However, the verification of actual device performance occurs late in that cycle. In contrast, the new methodology’s work flows can encompass the design and test of relevant electrical test structures early in the program. In this fashion, the relationship between materials properties and device performance can be validated empirically, and the model can be integrated and refined with each cycle of learning.
In the above post-CMP cleaning example, the customer’s device test structures were utilized to verify that the improvements in copper surface roughness and surface stability lead directly to improvements in device performance. This initial integration and device performance optimization work was performed in the high productivity development laboratory. Parametric testing of copper serpentine structures verified that the new post-CMP cleaning process was successfully integrated with adjacent process steps, and provided the expected improvement in copper line resistance. Parametric testing of interdigitated comb structures also showed an improvement in time dependent dielectic breakdown (TDDB). The reduction in TDDB was traced to an improvement in trace metal removal from the dielectric surface for the improved post-CMP cleaning formulation.
This early integration and device performance data provided a high level of confidence that the new post-CMP cleaning formulation could be successfully integrated into the customer’s HVM process flow. As a result, when the company scaled up the process, and performed qualification and final test, the required time was significantly reduced since many integration issues had already been resolved. Additional optimization of the HVM process could easily be performed due to the extensive set of characterization data that was generated by using this methodology.
Conclusion
A new technique has brought combinatorial methods much closer to semiconductor process applications while informing process development, process troubleshooting, and process integration. Combining the core capabilities of combinatorial tools with expertise in surface science allows many potential process and materials solutions to be screened intelligently in a fraction of the time, at significantly lower cost over conventional development methods. The capabilities also yield a rich information base that allows integrated circuit manufacturers to make prudent, data-driven decisions that mitigate risks regarding new processes and materials???in advance of the process freeze deadlines for manufacturing scale-up.
Reference
1. “The R&D Crisis,” VLSI Research; https://www.vlsiresearch.com/public/600201_r&d_crisis.pdf; 2005.
Joe Hillman received his BS degree in materials science and engineering from the Massachusetts Institute of Technology, and is director, high productivity development, at ATMI, Inc., 2151 East Broadway Road, Suite 101, Tempe AZ 85282, USA; ph.: 480-522-6917; email [email protected].